GROUND FAULT DETECTOR

• US 20190383871A1
• Filed: 08/30/2019
• Published: 12/19/2019
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Leviton Manufacturing Company Incorporated
• Original Assignee: Leviton Manufacturing Company Incorporated
• Inventors: OSTROVSKY, Michael, Aronov, Alek, Kamor, Michael, Mathew, Renjith
• Granted Patent: US 10,641,812 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/3277 of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
• CPC Class Codes: G01R 31/50 Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections testing of sparking plugs H01T13/58
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: H02H 3/335 the main function being self testing of the device

Abstract

An apparatus includes an interruption circuit in a power delivery path, and a fault detection circuit configured to provide a fault signal to selectively cause the interruption circuit to interrupt power delivery, wherein the fault detection circuit includes a fault detection integrated circuit and a sensing coil configured to sense a differential current between a phase conductive path and a neutral conductive path in the power delivery path. A processor is configured to selectively control a fault simulation circuit to simulate a fault in the power delivery path, detect a response of the fault detection circuit to the simulated fault, and determine if the response of the fault detection circuit is an expected response. The processor provides an override signal to the interruption circuit to prevent the interruption circuit from receiving a fault signal from the fault detection circuit during, and for a predetermined time after, the simulated fault.

Claims

1. An apparatus, comprising:

an interruption circuit electrically connected in a power delivery path, the power delivery path including a phase conductive path and a neutral conductive path;

a fault detection circuit coupled to the interruption circuit and configured to provide a fault signal to selectively cause the interruption circuit to interrupt power delivery in at least one of the phase conductive path and the neutral conductive path, wherein the fault detection circuit includes a sensing coil configured to sense a differential current between the phase conductive path and the neutral conductive path, and further includes a comparator-type fault detection integrated circuit (IC) that compares the differential current to a threshold;

a fault simulation circuit; and

a processor coupled to the fault simulation circuit and the fault detection circuit, the processor configured to

selectively control the fault simulation circuit to simulate a fault in the power delivery path;

detect a response of the fault detection circuit to the simulated fault; and

determine if the response of the fault detection circuit is an expected response;

wherein the processor provides an override signal to the interruption circuit to prevent the interruption circuit from receiving a fault signal from the fault detection circuit during, and for a predetermined time after, the simulated fault.

2. The apparatus of claim 1, wherein the processor is powered from the line side conductors.

3. The apparatus of claim 1, the processor further configured to:

receive an indication that the fault detection circuit has provided the fault signal;

receive an indication that a reset button has been pushed;

initiate a self-test including a fault simulation; and

if the self-test passes, provide a release signal to an electronic switch component to unlatch and thereby allow the interruption circuit to remove an interruption of power delivery; and

if the self-test does not pass, prevent the interruption circuit from removing the interruption of power delivery.

4. The apparatus of claim 1, further comprising a silicon-controlled rectifier (SCR), wherein power delivery is interrupted by the latching of the SCR in a conductive state in response to a received fault signal, and wherein the SCR is powered from a rectified power signal or an alternating current power line such that the SCR may only be latched during one power half-cycle;

the processor further configured to;

receive an indication that a manual reset button has been pushed;

initiate a self-test including self-testing in two power half-cycles of opposite polarity to ensure that the SCR will latch in response to a fault signal received during a self-test in one of the two power half-cycles.

5. The apparatus of claim 1, further comprising a rectifier, wherein the processor is configured to, prior to initiating a fault simulation, determine the rate of zero crossings of an amplitude of the output of the rectifier to identify a failure of a component in the rectifier, and if a failure of a component in the rectifier is detected, the processor does not initiate a fault simulation.

30. The apparatus of claim 1, wherein the predetermined time after the simulated fault is a non-zero time.

31. The apparatus of claim 1, wherein:

the fault detection circuit is configured to provide the fault signal to a specific node of the interruption circuit; and

the processor is configured to override the fault signal by providing the override signal to the specific node of the interruption circuit, to prevent the interruption circuit from receiving the fault signal.

32. The apparatus of claim 31, wherein the node of the interruption circuit is a terminal of a silicon-controlled rectifier (SCR) of the interruption circuit.

6. An apparatus, comprising:

an interruption circuit electrically connected in a power delivery path, the power delivery path including a phase conductive path and a neutral conductive path;

a fault detection circuit coupled to the interruption circuit and configured to provide a fault signal upon detection of a fault in the power delivery path;

a fault simulation circuit configured to selectively cause a current imbalance between the phase conductive path and the neutral conductive path; and

a processor coupled to the fault simulation circuit and the fault detection circuit, the processor configured to;

selectively control the fault simulation circuit to cause a first current imbalance to simulate a fault during a first power half-cycle; and

detect a response of the fault detection circuit to the simulated fault;

wherein the processor provides an override signal to the interruption circuit to prevent the interruption circuit from receiving a fault signal from the fault detection circuit during, and for a predetermined time after, the simulated fault.

7. The apparatus of claim 6, wherein the processor is configured to selectively control the fault simulation circuit to cause the first current imbalance starting at a predetermined time after the beginning of the first power half-cycle.

8. The apparatus of claim 6, wherein the first power half-cycle is randomly either a positive polarity or a negative polarity.

9. The apparatus of claim 6, wherein the processor is configured to control the fault simulation circuit to cause a second current imbalance during a second power half-cycle.

10. The apparatus of claim 9, wherein the first power half-cycle and the second power half-cycle have approximately opposite polarity.

11. The apparatus of claim 9, wherein the end of the first power half-cycle and the beginning of the second power half-cycle are separated in time by an even number of power half-cycles.

12. The apparatus of claim 9, wherein the processor is configured to control the fault simulation circuit to cause the first current imbalance during a portion of the first power half-cycle and to cause a second current imbalance during a portion of the second power half-cycle, each portion beginning several milliseconds after the start of the respective half-cycle.

33. The apparatus of claim 6, wherein the predetermined time after the simulated fault is a non-zero time.

34. The apparatus of claim 6, wherein:

the fault detection circuit is configured to provide the fault signal to a specific node of the interruption circuit; and

the processor is configured to override the fault signal by providing the override signal to the specific node of the interruption circuit, to prevent the interruption circuit from receiving the fault signal.

35. The apparatus of claim 34, wherein the node of the interruption circuit is a terminal of a silicon-controlled rectifier (SCR) of the interruption circuit.

36. The apparatus of claim 11, wherein the even number is two or greater.

13-29. -29. (canceled)