SHIFT REGISTER AND TOUCH DISPLAY APPARATUS THEREOF
First Claim
1. A shift register for generating a plurality of shifted pulse signals shifted by a specified phase, the shift register comprising:
- a plurality of cascade-connected unit circuits, each unit circuit configured to receive a clock control signal, and each unit circuit comprising;
an output terminal, electrically coupled to at least one external signal line, and configured to provide a shifted pulse signal to the connected at least one external signal line;
an input transistor, controlled by a first control signal, and configured to output a high-level voltage to a first node based on a trigger signal for activating the unit circuit;
an output transistor, including a first control terminal connected to the first node, a first connection terminal receiving the clock control signal, and a second connection terminal connected to the output terminal, the output transistor outputting the shifted pulse signal to the output terminal in response to the high-level voltage of the first node, the shifted pulse signal being synchronous with the clock control signal; and
a pull-up transistor, including a second control terminal connected to the output terminal, a third connection terminal connected to the second control terminal, and a fourth connection terminal connected to a high voltage power source;
wherein the shifted pulse signal of the (N+1)th unit circuit outputted to the (N+1)th signal line is shifted by a specified phase by compared to the shifted pulse signal of the Nth unit circuit outputted to the Nth signal line;
a blank period is inserted between two adjacent shifted pulse signals of two adjacent unit circuits;
during the (N+1)th unit circuit outputting the shifted pulse signal after the blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage.
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Accused Products
Abstract
A shift register driving a touch display device generates shifted pulse signals shifted by a specified phase. The shift register includes unit circuits connected in multiple stages. Each unit circuit includes an output terminal, an input transistor, an output transistor, and a pull-up transistor. The input transistor is controlled by a first control signal and outputs a high-level voltage to a first node based on the value of a trigger signal. The output transistor outputs the shifted pulse signal, which is synchronous with a clock control signal, based on the value of the high-level voltage of the first node. A blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit. After the blank period, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage.
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13 Claims
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1. A shift register for generating a plurality of shifted pulse signals shifted by a specified phase, the shift register comprising:
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a plurality of cascade-connected unit circuits, each unit circuit configured to receive a clock control signal, and each unit circuit comprising; an output terminal, electrically coupled to at least one external signal line, and configured to provide a shifted pulse signal to the connected at least one external signal line; an input transistor, controlled by a first control signal, and configured to output a high-level voltage to a first node based on a trigger signal for activating the unit circuit; an output transistor, including a first control terminal connected to the first node, a first connection terminal receiving the clock control signal, and a second connection terminal connected to the output terminal, the output transistor outputting the shifted pulse signal to the output terminal in response to the high-level voltage of the first node, the shifted pulse signal being synchronous with the clock control signal; and a pull-up transistor, including a second control terminal connected to the output terminal, a third connection terminal connected to the second control terminal, and a fourth connection terminal connected to a high voltage power source; wherein the shifted pulse signal of the (N+1)th unit circuit outputted to the (N+1)th signal line is shifted by a specified phase by compared to the shifted pulse signal of the Nth unit circuit outputted to the Nth signal line;
a blank period is inserted between two adjacent shifted pulse signals of two adjacent unit circuits;during the (N+1)th unit circuit outputting the shifted pulse signal after the blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A touch display apparatus comprising:
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a display region; and a non-display region surrounding the display region, and the non-display region comprising; at least one gate driver with at least one shift register disposed in the non-display region;
the shift register comprising a plurality of cascade-connected unit circuits, and configured to generate a plurality of shifted pulse signals shifted by a specified phase shift;
each unit circuit configured to receive an clock control signal, each of the unit circuit comprising;an output terminal, electrically coupled to at least one external signal line, and configured to provide a shifted pulse signal to the connected at least one external signal line; an input transistor, controlled by a first control signal, and configured to output a high-level voltage to a first node based on a trigger signal activating the unit circuit; an output transistor, including a first control terminal connected to the first node, a first connection terminal receiving the clock control signal, and a second connection terminal connected to the output terminal, the output transistor outputting the shifted pulse signal to the output terminal in response to the high-level voltage of the first node, the shifted pulse signal being synchronous with the clock control signal; and a pull-up transistor, including a second control terminal connected to the output terminal, a third connection terminal connected to the second control terminal, and a fourth connection terminal connected to a high voltage power source; wherein the shifted pulse signal of the (N+1)th unit circuit outputted to the (N+1)th signal line is shifted a specified phase by compared to the shifted pulse signal of the Nth unit circuit outputted to the Nth signal line;
a blank period is inserted between two adjacent shifted pulse signals of two adjacent unit circuits;
during the (N+1)th unit circuit outputting the shifted pulse signal after the blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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Specification