TECHNIQUES FOR SETTING A 2-LEVEL AUTO-CLOSE TIMER TO ACCESS A MEMORY DEVICE
First Claim
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1. An apparatus comprising:
- an interface of a memory controller to access memory devices via multiple channels; and
circuitry of the memory controller to;
set a first time value for a first level of a 2-level auto-close timer, the first level of the 2-level auto-close timer to cause a row of a bank of first memory devices to auto-close following a first cache line access to the row responsive to a multi-channel address interleave policy that causes successive cache line accesses to the bank of first memory devices via a first channel of the multiple channels; and
set a second time value for a second level of the 2-level auto-close timer, the second level of the 2-level auto-close timer to cause the row to auto-close following a second cache line access to the row responsive to the multi-channel address interleave policy that causes non-successive cache line accesses to the bank of first memory devices via the first channel.
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Abstract
Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.
3 Citations
21 Claims
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1. An apparatus comprising:
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an interface of a memory controller to access memory devices via multiple channels; and circuitry of the memory controller to; set a first time value for a first level of a 2-level auto-close timer, the first level of the 2-level auto-close timer to cause a row of a bank of first memory devices to auto-close following a first cache line access to the row responsive to a multi-channel address interleave policy that causes successive cache line accesses to the bank of first memory devices via a first channel of the multiple channels; and set a second time value for a second level of the 2-level auto-close timer, the second level of the 2-level auto-close timer to cause the row to auto-close following a second cache line access to the row responsive to the multi-channel address interleave policy that causes non-successive cache line accesses to the bank of first memory devices via the first channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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setting a first time value for a first level of a 2-level auto-close timer, the first level of the 2-level auto-close timer to cause a row of a bank of first memory devices to auto-close following a first cache line access to the row responsive to a multi-channel address interleave policy that causes successive cache line accesses to the bank of first memory devices via a first channel coupled with a processor; and setting a second time value for a second level of the 2-level auto-close timer, the second level of the 2-level auto-close timer to cause the row to auto-close following a second cache line access to the row responsive to the multi-channel address interleave policy that causes non-successive cache line accesses to the bank of first memory devices via the first channel. - View Dependent Claims (13, 14, 15, 16)
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17. At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system, cause the system to:
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set a first time value for a first level of a 2-level auto-close timer, the first level of the 2-level auto-close timer to cause a row of a bank of first memory devices to auto-close following a first cache line access to the row responsive to a multi-channel address interleave policy that causes successive cache line accesses to the bank of first memory devices via a first channel coupled with a processor; and set a second time value for a second level of the 2-level auto-close timer, the second level of the 2-level auto-close timer to cause the row to auto-close following a second cache line access to the row responsive to the multi-channel address interleave policy that causes non-successive cache line accesses to the bank of first memory devices via the first channel. - View Dependent Claims (18, 19, 20, 21)
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Specification