MACHINE PERCEPTION AND DENSE ALGORITHM INTEGRATED CIRCUIT

• US 20200034082A1
• Filed: 10/02/2019
• Published: 01/30/2020
• Est. Priority Date: 03/08/2018
• Status: Active Grant

• Current Assignee: quadric.io, Inc.
• Original Assignee: quadric.io, Inc.
• Inventors: Drego, Nigel, Sikka, Aman, Ravichandran, Mrinalini, Durbha, Ananth, Firu, Robert Daniel, Kheterpal, Veerbhan
• Granted Patent: US 10,642,541 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/32 Circuit design at the digital level reconfigurable circuits G06F30/34
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level

Abstract

A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.

Claims

1. An integrated circuit comprising:

a plurality of array cores, each array core of the plurality of array cores comprising;

a plurality of distinct data processing circuits, at least one of the plurality of distinct data processing circuits being arranged along each interior side of each array core; and

a data queue register file;

wherein;

a combination of the plurality of array cores define an integrated circuit array.

2. The integrated circuit according to claim 1, further comprising:

a plurality of border cores, each border core of the plurality of border cores comprising;

at least a register file, wherein;

[i] a combination of the plurality of array cores and the plurality of border cores define the integrated circuit array; and

[ii] a subset of the plurality of border cores define one or more peripheral sides of the integrated circuit array.

3. The integrated circuit according to claim 1, wherein

the plurality of distinct processing circuits of each of the plurality of array cores comprises:

a plurality of multiply accumulators, each of the plurality of multiply accumulators being arranged adjacent a data input/output port of a respective array core of the plurality of array cores.

4. The integrated circuit according to claim 1, wherein

the plurality of distinct data processing circuits surround the data queue register file.

5. The integrated circuit according to claim 1, wherein

each of the plurality of array cores further comprises at least one arithmetic logic unit.

6. The integrated circuit according to claim 5, wherein:

the at least one arithmetic logic unit is arranged adjacent the data queue register file, and

the plurality of distinct data processing circuits surround the data queue register file and the arithmetic logic unit.

7. The integrated circuit according to claim 1, wherein

a first subset of the plurality of array cores encompasses a periphery of a second subset of the plurality of array cores.

8. The integrated circuit according to claim 1, further comprising:

a first plurality of dual FIFOs that load data into the integrated circuit array on a first-in, first-out basis, such that an oldest dataset entering a respective dual FIFO of the first plurality of dual FIFOs is first disposed by the respective dual FIFO,

wherein the first plurality of dual FIFOs are arranged along a first peripheral side of the integrated circuit array;

a second plurality of dual FIFOs that load data into the integrated circuit array on a first-in, first-out basis, such that an oldest dataset entering a respective dual FIFO of the second plurality of dual FIFOs is first disposed by the respective dual FIFO,

wherein the second plurality of dual FIFOs are arranged along a second peripheral side of the integrated circuit array that is distinct from the first peripheral side of the integrated circuit array.

9. The integrated circuit according to claim 2, further comprising:

a first plurality of dual FIFOs that load data into the integrated circuit array on a first-in, first-out basis, wherein;

the first plurality of dual FIFOs are arranged along a first peripheral border of the integrated circuit array,

the first peripheral border being defined by a subset of the plurality of border cores, and

each of the first plurality of dual FIFOs loads data directly into an adjacent one of the subset of the plurality of border cores.

10. The integrated circuit according to claim 9, further comprising:

a second plurality of dual FIFOs that load data into the integrated circuit array on a first-in, first-out basis, wherein;

the second plurality of dual FIFOs are arranged along a second peripheral border of the integrated circuit array,

the second peripheral border being defined by a distinct subset of the plurality of border cores, and

each of the second plurality of dual FIFOs loads data directly into an adjacent one of the distinct subset of the plurality of border cores.

11. The integrated circuit according to claim 8, wherein:

each of the first and the second plurality of dual FIFOs comprise at least two memory elements;

a first of the at least two memory elements pushes data into one of a border core of the plurality of border cores and an array core of the plurality of array cores of the integrated circuit array;

a second of the at least two memory elements collects data from the one of a border core of the plurality of border cores and an array core of the plurality of array cores of the integrated circuit array.

12. The integrated circuit according to claim 3, wherein:

each of the plurality of array cores having a rectangular shape; and

each one of the plurality of multiply accumulators being arranged along one side of the rectangular shape of each of the plurality of array cores.

13. The integrated circuit according to claim 1, further comprising:

a first periphery memory and a second periphery memory that interface with unified memory, wherein;

the first periphery memory is arranged along a first peripheral side of the integrated circuit array and interfaces with a first periphery load store; and

the second periphery memory is arranged along a second peripheral side of the integrated circuit array and interfaces with a second periphery load store.

14. The integrated circuit according to claim 1, further comprising:

a hierarchical memory structure that enables direct memory access between a main memory and the integrated circuit array, the hierarchical memory structure includes;

a plurality of dual FIFOs that interface with the integrated circuit array and transmit and accept data on a first-in, first-out basis,

a plurality of periphery load store that each interface with a respective dual FIFO of the plurality of dual FIFOs and store one or more loads of data that is either received from the respective dual FIFO or that is pending a loading into the respective dual FIFO, and

a plurality of periphery memory that each interface with a respective periphery load store of the plurality of periphery load stores and interfaces with the main memory.

15. The integrated circuit according to claim 1, further comprising:

a plurality of periphery controllers that, when executing data movement instructions, control a movement of data between the hierarchical memory structure and the integrated circuit array.

16. The integrated circuit according to claim 14, wherein

the hierarchical memory structure being implemented as a two-dimensional direct memory access enabling data access and data reshaping during data transfers.

17. The integrated circuit according to claim 2, further comprising:

a dispatch controller that provides;

(i) data movement instructions that causes an automatic movement of data;

(a) between a hierarchical memory structure of the integrated circuit and the integrated circuit array;

(b) within each respective array core of the plurality of array cores;

(c) between respective array cores and between array cores and border cores of the integrated circuit array; and

(ii) computation instructions that define a plurality of computations to be executed by the plurality of array cores of the integrated circuit array.

18. The integrated circuit according to claim 2, further comprising:

a dispatch controller that provides data movement instructions, wherein the data movement instructions comprise a data flow schedule that;

(i) defines an automatic movement of data within the integrated circuits; and

(ii) sets one or more border cores of the plurality of border cores to a predetermined constant value if no data is provided to the one or more border cores according to the predetermined data flow schedule.

wherein the data flow schedule comprises a schedule of memory addresses executable by one or more of a plurality of periphery load stores.

19. The integrated circuit according to claim 1, further comprising:

a dispatch controller comprising;

a compute instructions generator circuit that provides computation instructions for each of the plurality of array cores; and

a data movement generator circuit that provides a data flow schedule that defines predetermined movements of data within the integrated circuit.

20. The integrated circuit according to claim 1, further comprising:

a broadcast bus arranged in electrical communication with one or more periphery controllers at a first input terminal of the broadcast bus and in electrical communication with a subset of the plurality of array cores at a plurality of output terminals of the broadcast bus.