ELECTROSTATIC DISCHARGE PROTECTION APPARATUS HAVING AT LEAST ON JUNCTION AND METHOD FOR OPERATING THE SAME

• US 20200051970A1
• Filed: 08/08/2018
• Published: 02/13/2020
• Est. Priority Date: 08/08/2018
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: WANG, Shih-Yu, LEE, Ming-Yin
• Granted Patent: US 10,643,989 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/861 Diodes

Abstract

An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region, a fourth doping region and at least one junction formed by different conductivities. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the first conductivity is disposed in the first well. The second doping region having the second conductivity is disposed in the first well. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The at least one junction is formed by the first doping region and the second doping region, or formed by the third doping region and the fourth doping region.

Claims

1. An electrostatic discharge (ESD) protection apparatus, comprising:

a semiconductor substrate;

a first well having a first conductivity, disposed in the semiconductor substrate;

a second well having a second conductivity, disposed in the semiconductor substrate;

a first doping region having the first conductivity and disposed in the first well;

a second doping region having the second conductivity and disposed in the first well;

a third doping region having the first conductivity, disposed in the second well;

a fourth doping region having the second conductivity, disposed in the second well;

a first junction formed by the first doping region and the second doping region; and

a second junction formed by the third doping region and the fourth doping region,

wherein at least one of the first doping region, the second doping region, the third doping region and the fourth doping region is in a floating state, ESD current flows through the at least one of the first doping region, the second doping region, the third doping region and the fourth doping region in the floating state.

2. The ESD protection apparatus according to claim 1, wherein the second doping region, the first well and the second well are integrated to form a first parasitic bipolar junction transistor (BJT);

the first well, the third doping region and the second well are integrated to form a second parasitic BJT; and

the first parasitic BJT and the second parasitic BJT have different majority carriers.

3. The ESD protection apparatus according to claim 1, wherein the first conductivity is n-type conductivity, and the second conductivity is p-type conductivity;

the first doping region is connected to a voltage source, and the fourth doping region is connected to a ground.

4. The ESD protection apparatus according to claim 3, wherein the second doping region is in the floating state, and the third doping region is connected to the ground.

5. The ESD protection apparatus according to claim 4, further comprising a fifth doping region, having the first conductivity and disposed in the first well, and connected to the second doping region.

6. The ESD protection apparatus according to claim 4, further comprising a fifth doping region, having the second conductivity and disposed between the second doping region and the third doping region.

7. The ESD protection apparatus according to claim 6, wherein a portion of the fifth doping region is disposed in the first well and the other portion of the fifth doping region is disposed in the second well.

8. The ESD protection apparatus according to claim 3, wherein the second doping region is connected to the voltage source, and the third doping region is in the floating state.

9. The ESD protection apparatus according to claim 8, further comprising a fifth doping region, having the second conductivity and disposed in the second well, and connected to the third doping region.

10. (canceled)

11. A method for operating an ESD protection apparatus, comprising:

providing an ESD protection apparatus electrically connected to an internal circuit, the ESD protection apparatus comprising;

a semiconductor substrate;

a first well having a first conductivity, disposed in the semiconductor substrate;

a second well having a second conductivity, disposed in the semiconductor substrate;

a first doping region having the first conductivity and disposed in the first well;

a second doping region having the second conductivity and disposed in the first well;

a third doping region having the first conductivity, disposed in the second well;

a fourth doping region having the second conductivity, disposed in the second well;

a first junction formed by the first doping region and the second doping region; and

a second junction formed by the third doping region and the fourth doping region,

wherein at least one of the first doping region, the second doping region, the third doping region and the fourth doping region is in a floating state,

when the internal circuit is subjected to an ESD stress, directing ESD current to a ground by the ESD protection apparatus through the at least one of the first doping region, the second doping region, the third doping region and the fourth doping region in the floating state, the first junction and the second junction.

12. The method according to claim 11, wherein the second doping region, the first well and the second well are integrated to form a first parasitic bipolar junction transistor (BJT);

the first well, the third doping region and the second well are integrated to form a second parasitic BJT; and

the first parasitic BJT and the second parasitic BJT have different majority carriers.

13. The method according to claim 11, wherein the first conductivity is n-type conductivity, and the second conductivity is p-type conductivity;

the ESD current flows into the ESD protection apparatus through the first doping region, and is directed into the ground via the third doping region.

14. The method according to claim 11, further comprising remaining the second doping region in the floating state, when the internal circuit is subjected to the ESD stress.

15. The method according to claim 13, wherein the ESD protection apparatus further comprises a fifth doping region having the second conductivity disposed between the second doping region and the third doping region.

16. The method according to claim 15, wherein a portion of the fifth doping region is disposed in the first well and the other portion of the fifth doping region is disposed in the second well.

17. The method according to claim 11, wherein the first conductivity is n-type conductivity, and the second conductivity is p-type conductivity;

the ESD current flows into the ESD protection apparatus through the second doping region, and is directed into the ground via the fourth doping region.

18. The method according to claim 11, further comprising remaining the third doping region in the floating state, when the internal circuit is subjected to the ESD stress.