LOW-SPEED MEMORY OPERATION

• US 20200073562A1
• Filed: 09/04/2018
• Published: 03/05/2020
• Est. Priority Date: 09/04/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kim, Kang-Yong
• Granted Patent: US 10,642,512 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal. Such techniques may provide improved data bandwidth, improved command bandwidth, and/or reduced power consumption.

Claims

1. A method, comprising:

identifying a clock mode for a system clock that generates a system clock signal, wherein a first memory die and a second memory die are each configured to receive the system clock signal and a common data clock signal;

generating an internal data clock signal for the first memory die; and

routing the internal data clock signal to a data clock tree of the first memory die based at least in part on identifying the clock mode.

2. The method of claim 1, further comprising:

activating an internal data clock for the first memory die based at least in part on identifying the clock mode, wherein the internal data clock is configured to generate the internal data clock signal.

3. The method of claim 2, further comprising:

deactivating the internal data clock based at least in part on, after activating the internal data clock, identifying a second clock mode for the system clock.

4. The method of claim 1, further comprising:

disconnecting a common data clock, wherein the common data clock generates the common data clock signal, from the data clock tree of the first memory die based at least in part on identifying the clock mode.

5. The method of claim 1, further comprising:

identifying a second clock mode for the system clock; and

routing the common data clock signal to the data clock tree of the first memory die based at least in part on identifying the second clock mode.

6. The method of claim 1, further comprising:

deactivating a common data clock, wherein the common data clock generates the common data clock signal, based at least in part on identifying the clock mode.

7. The method of claim 1, further comprising:

deactivating a common control signal for the first memory die and the second memory die based at least in part on identifying the clock mode.

8. The method of claim 1, further comprising:

adjusting a burst length of an access operation related to memory cells included in the first memory die based at least in part on identifying the clock mode.

9. The method of claim 1, wherein generating the internal data clock signal comprises:

generating the internal data clock signal having a shorter period than the common data clock signal.

10. The method of claim 1, wherein generating the internal data clock signal comprises:

generating the internal data clock signal having a shorter period than the system clock signal.

11. The method of claim 10, wherein identifying the clock mode comprises:

identifying the system clock signal as having a first speed, wherein the system clock signal supports at least the first speed and a second speed that is greater than the first speed.

12. The method of claim 10, further comprising:

performing an access operation for memory cells included in the first memory die, the access operation based at least in part on the internal data clock signal, and the access operation having a duration less than two periods of the system clock signal.

13. The method of claim 1, wherein identifying the clock mode comprises:

determining that a mode register for the first memory die indicates a speed of the system clock.

14. A method, comprising:

identifying a system clock speed as below a threshold, the system clock speed being associated with a system clock signal that is common to a first memory die and a second memory die;

disconnecting a common data clock from a data clock tree of the first memory die based at least in part on identifying the system clock speed as below the threshold, the common data clock generating a common data clock signal that is common to the first memory die and the second memory die; and

connecting an internal data clock within the first memory die to the data clock tree based at least in part on identifying the system clock speed as below the threshold.

15. The method of claim 14, further comprising:

activating the internal data clock based at least in part on identifying the system clock speed as below the threshold.

16. The method of claim 14, further comprising:

performing an access operation, based at least in part on the internal data clock, on memory cells included in the first memory die, wherein the access operation has a duration that is less than two periods of the system clock signal.

17. The method of claim 16, wherein the duration is less than one period of the system clock signal.

18. The method of claim 14, further comprising:

generating, by the internal data clock, an internal data clock signal having a first period that is shorter than a second period of the common data clock signal.

19. The method of claim 14, further comprising:

after identifying the system clock speed as below the threshold, identifying the system clock speed as above the threshold;

connecting the common data clock to the data clock tree of the first memory die based at least in part on identifying the system clock speed as above the threshold;

disconnecting the internal data clock from the data clock tree based at least in part on identifying the system clock speed as above the threshold; and

deactivating the internal data clock based at least in part on identifying the system clock speed as above the threshold.

20. An apparatus, comprising:

a first memory die configured to receive a common data clock signal that is common to the first memory die and a second memory die;

an internal data clock included in the first memory die and configured to generate an internal data clock signal for the first memory die; and

a selection component configured to route the common data clock signal or the internal data clock signal to a data clock tree of the first memory die based at least in part on a mode of operation of the first memory die.

21. The apparatus of claim 20, further comprising:

a mode identification component configured to identify the mode of operation of the first memory die and enable the internal data clock based at least in part on identifying the mode of operation as a first mode of operation.

22. The apparatus of claim 21, wherein the mode identification component is configured to disable the internal data clock based at least in part on identifying the mode of operation as a second mode of operation.

23. The apparatus of claim 20, wherein:

the selection component is configured to route the internal data clock signal to the data clock tree of the first memory die when the mode of operation corresponds to a first system clock speed; and

the selection component is configured to route the common data clock signal to the data clock tree of the first memory die when the mode of operation corresponds to a second system clock speed that is greater than the first system clock speed.

24. The apparatus of claim 20, further comprising:

a common system clock that is coupled with the first memory die and the second memory die; and

a mode register configured to store an indication of a speed of the common system clock, wherein the mode of operation corresponds to the speed of the common system clock.

25. The apparatus of claim 20, wherein the internal data clock signal has a shorter period than the common data clock signal.

26. The apparatus of claim 20, further comprising:

a controller that is common to the first memory die and the second memory die, wherein the controller is configured to disable the common data clock signal based at least in part on the mode of operation.

27. The apparatus of claim 20, wherein the internal data clock comprises an oscillator included within the first memory die, the apparatus further comprising:

a regulated power supply configured to power the oscillator.

28. An apparatus, comprising:

a first memory die configured to receive a system clock signal and a common data clock signal;

a second memory die configured to receive the system clock signal and the common data clock signal;

an internal data clock included in the first memory die and configured to generate an internal data clock signal for the first memory die, wherein the internal data clock signal has a first period and the common data clock signal has a second period that is longer than the first period; and

a selection component included in the first memory die, the selection component configured to select the common data clock signal or the internal data clock signal based at least in part on a speed of the system clock signal.

29. The apparatus of claim 28, wherein:

the selection component is configured to select the internal data clock signal when the speed of the system clock signal is at a minimum speed supported by the system clock signal; and

the selection component is configured to select the common data clock signal when the speed of the system clock signal is at a maximum speed supported by the system clock signal.

30. The apparatus of claim 28, further comprising:

a data clock tree included in the first memory die, wherein the data clock tree is configured to receive a data clock signal selected by the selection component.

31. The apparatus of claim 28, further comprising:

an activation component configured to;

activate the internal data clock based at least in part on identifying the speed of the system clock signal as a minimum speed supported by the system clock signal; and

deactivate the internal data clock based at least in part on identifying the speed of the system clock signal as a maximum speed supported by the system clock signal.

32. An apparatus, comprising:

a first memory die configured to receive a system clock signal and a common data clock signal;

a second memory die configured to receive the system clock signal and the common data clock signal; and

a controller configured to;

set a speed of the system clock signal to a first speed, wherein the system clock signal supports the first speed and a second speed greater than the first speed; and

disable the common data clock signal based at least in part on setting the speed of the system clock signal to the first speed.

33. The apparatus of claim 32, wherein the controller is further configured to:

set a first mode register included in the first memory die to indicate that the speed of the system clock signal is set to the first speed; and

set a second mode register included in the second memory die to indicate that the speed of the system clock signal is set to the second speed.

34. The apparatus of claim 32, wherein the controller is further configured to:

set a burst length of an access operation for memory cells included in the first memory die based at least in part on setting the speed of the system clock signal to the first speed.

35. The apparatus of claim 34, wherein setting the burst length of the access operation comprises:

setting a first mode register included in the first memory die to indicate the burst length of the access operation.