SEMICONDUCTOR MEMORY DEVICE

• US 20200090771A1
• Filed: 02/14/2019
• Published: 03/19/2020
• Est. Priority Date: 09/13/2018
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Umezawa, Yusuke
• Granted Patent: US 10,643,723 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

At a time of writing first data to a first memory cell, second data which is written later to an adjacent second memory cell is referred to, and when a value of the second data corresponds to a first threshold level, a verify voltage is set to a first verify voltage, and when the value of the second data corresponds to a second threshold level greater than the first threshold level, the verify voltage is set to a second verify voltage smaller than the first verify voltage.

Claims

1. A semiconductor memory device comprising:

a substrate;

a memory cell array including a plurality of memory cells arrayed in a first direction crossing the substrate and a second direction crossing the first direction, the memory cells being capable of storing data indicating a plurality of values corresponding to a plurality of threshold levels; and

a control circuit that applies a predetermined voltage to the memory cells to change threshold voltages of the memory cells to a threshold level corresponding to a value of data to be stored respectively, and terminates writing of the data when the threshold level of the memory cells exceeds a predetermined verify voltage, wherein

the memory cell array includes a first memory cell in which first data is stored and a second memory cell adjacent to the first memory cell and in which second data is written after the writing to the first memory cell, and

the control circuit refers to the second data at a time of writing the first data to the first memory cell, and when a value of the second data corresponds to a first threshold level, sets the verify voltage to a first verify voltage, and when the value of the second data corresponds to a second threshold level greater than the first threshold level, sets the verify voltage to a second verify voltage smaller than the first verify voltage.

2. The semiconductor memory device according to claim 1, wherein

when the value of the second data corresponds to a third threshold level greater than the second threshold level, the control circuit sets the verify voltage to the second verify voltage, and when the value of the second data corresponds to a fourth threshold level greater than the third threshold level, sets the verify voltage to the second verify voltage.

3. The semiconductor memory device according to claim 1, wherein

when the value of the second data corresponds to a third threshold level greater than the second threshold level, the control circuit sets the verify voltage to a third verify voltage smaller than the second verify voltage, and when the value of the second data corresponds to a fourth threshold level greater than the third threshold level, sets the verify voltage to a fourth verify voltage smaller than the third verify voltage.

4. The semiconductor memory device according to claim 1, wherein

the first memory cell and the second memory cell are disposed at substantially the same position in the first direction, and are adjacent to each other in the second direction.

5. The semiconductor memory device according to claim 4, further comprising:

a first conductive layer; and

a second conductive layer disposed apart from the first conductive layer in the second direction, wherein

the first memory cell and the second memory cell are disposed between the first conductive layer and the second conductive layer,

the first memory cell is connected to the first conductive layer, and

the second memory cell is connected to the second conductive layer.

6. The semiconductor memory device according to claim 4, wherein

the memory cell array further includes a third memory cell in which third data is stored and a fourth memory cell in which fourth data is written after the writing to the third memory cell,

the third memory cell and the fourth memory cell are adjacent to each other in the second direction,

a distance between the first memory cell and the second memory cell is smaller than a distance between the third memory cell and the fourth memory cell, and

the control circuit refers to the fourth data at a time of writing the third data to the third memory cell, and when a value of the fourth data corresponds to the first threshold level, sets the verify voltage to be applied to the third memory cell to the first verify voltage, and when the value of the fourth data corresponds to the second threshold level, sets the verify voltage to be applied to the third memory cell to a fifth verify voltage smaller than the first verify voltage and greater than the second verify voltage.

7. The semiconductor memory device according to claim 6, wherein

the third memory cell and the fourth memory cell are disposed at different positions in the first direction from the first memory cell and the second memory cell, and

the first memory cell and the second memory cell are closer to the substrate than the third memory cell and the fourth memory cell.

8. The semiconductor memory device according to claim 1, wherein

the memory cells each store data corresponding to a plurality of bits,

the control circuit repeatedly writes and verifies data to the first memory cell until the writing of the first data is completed, and after the writing of the first data to the first memory cell is completed, executes writing the second data to the second memory cell of an erased state.

9. The semiconductor memory device according to claim 1, wherein

the memory cells each store data corresponding to a plurality of bits, a specific bit of the data indicates which one of the lower threshold level range and the higher threshold level range of the plurality of threshold levels,

the control circuit refers to the specific bit of the second data at a time of writing the first data to the first memory cell, when a value of the specific bit indicates the lower threshold level range, sets the verify voltage to the first verify voltage, and when the value of the specific bit indicates the higher threshold level range, sets the verify voltage to the second verify voltage.

10. The semiconductor memory device according to claim 1, wherein

the control circuit executes, after an initial writing operation to the first memory cell, an initial writing operation to the second memory cell, then executes a final writing operation to the first memory cell, and at a time of the final writing operation, refers to the second data, and sets the verify voltage to the first verify voltage or the second verify voltage according to the value of the second data.

11. A semiconductor memory device comprising:

a substrate;

a memory cell array including;

a first memory string including a plurality of memory cells connected in series in a first direction crossing the substrate;

a second memory string including a plurality of memory cells connected in series in the first direction, and being adjacent to the first memory string in a second direction crossing the first direction;

a plurality of first conductive layers respectively connected to the memory cells of the first memory string and arranged in the first direction;

a plurality of second conductive layers respectively connected to the memory cells of the second memory string and arranged in the first direction; and

a third conductive layer connected to one end of the first memory string, the memory cells being capable of storing data indicating a plurality of values corresponding to a plurality of threshold levels; and

a control circuit that applies a predetermined voltage to the first to third conductive layers according to a plurality of writing steps, to change threshold voltages of the memory cells to a threshold level corresponding to a value of data to be stored respectively, and performs a final writing step to terminate writing of the data to a certain memory cell when the threshold level of the certain memory cell exceeds a predetermined verify voltage, wherein

the memory cell array includes a first memory cell in which first data is stored and a second memory cell adjacent to the first memory cell and in which second data is written after the writing to the first memory cell, the first memory cell being included in the first memory string, and

the control circuit refers to the second data at a time of writing the first data to the first memory cell, and when a value of the second data corresponds to a first threshold level, sets a voltage to be applied to the third conductive layer in the final writing step to a first voltage, and when the value of the second data corresponds to a second threshold level greater than the first threshold level, sets the voltage to be applied to the third conductive layer in the final writing step to a second voltage greater than the first voltage.

12. The semiconductor memory device according to claim 11, wherein

the control circuit sets the voltage to be applied to the third conductive layer in the final writing step to the second voltage when the value of the second data corresponds to a third threshold level greater than the second threshold level, and sets the voltage to be applied to the third conductive layer in the final writing step to the second voltage when the value of the second data corresponds to a fourth threshold level greater than the third threshold level.

13. The semiconductor memory device according to claim 11, wherein

the control circuit sets the voltage to be applied to the third conductive layer in the final writing step to a third voltage greater than the second voltage when the value of the second data corresponds to a third threshold level greater than the second threshold level, and sets the voltage to be applied to the third conductive layer in the final writing step to a fourth voltage greater than the third voltage when the value of the second data corresponds to a fourth threshold level greater than the third threshold level.

14. The semiconductor memory device according to claim 11, wherein

the first memory cell and the second memory cell are disposed at substantially the same position in the first direction, and are adjacent to each other in the second direction.

15. The semiconductor memory device according to claim 11, wherein

the first memory string and the second memory string are disposed between the first conductive layers and the second conductive layers.

16. The semiconductor memory device according to claim 14, wherein

the memory cell array further includes a third memory cell in which third data is stored and a fourth memory cell in which fourth data is written after the writing to the third memory cell, the third memory cell being included in the first memory string,

the third memory cell and the fourth memory cell are adjacent to each other in the second direction,

a distance between the first memory cell and the second memory cell is smaller than a distance between the third memory cell and the fourth memory cell,

the control circuit refers to the fourth data at a time of writing the third data to the third memory cell, and when a value of the fourth data corresponds to the first threshold level, sets the voltage to be applied to the third conductive layer in the final writing step of the third memory cell to the first voltage, and when the value of the fourth data corresponds to the second threshold level, sets the voltage to be applied to the third conductive layer in the final writing step of the third memory cell to a fifth voltage greater than the first voltage and smaller than the second voltage.

17. The semiconductor memory device according to claim 16, wherein

the third memory cell and the fourth memory cell are disposed at different positions in the first direction from the first memory cell and the second memory cell, and

the first memory cell and the second memory cell are closer to the substrate than the third memory cell and the fourth memory cell.

18. The semiconductor memory device according to claim 11, wherein

the memory cells each store data corresponding to a plurality of bits,

the control circuit repeatedly writes and verifies data to the first memory cell until the writing of the first data is completed, and after the writing of the first data to the first memory cell is completed, executes writing the second data to the second memory cell of an erased state.

19. The semiconductor memory device according to claim 11, wherein

the memory cells each store data corresponding to a plurality of bits, a specific bit of the data indicates which one of the lower threshold level range and the higher threshold level range of the plurality of threshold levels,

the control circuit refers to the specific bit of the second data at a time of writing the first data to the first memory cell, when a value of the specific bit indicates the lower threshold level range, sets the voltage to be applied to the third conductive layer in the final writing step to the first voltage, and when the value of the specific bit indicates the higher threshold level range, sets the voltage to be applied to the third conductive layer in the final writing step to the second voltage.

20. The semiconductor memory device according to claim 11, wherein

the control circuit executes, after an initial writing operation to the first memory cell, an initial writing operation to the second memory cell, then executes a final writing operation to the first memory cell, and at a time of the final writing operation, refers to the second data, and sets the first voltage or the second voltage as the voltage to be applied to the third conductive layer in the final writing step according to the value of the second data.