SELF-CLOCKING SAMPLER WITH REDUCED METASTABILITY
First Claim
1. A self-clocked sampler system, comprising:
- a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals;
a detection circuit that is coupled to the sampler circuit and configured to;
pre-charge the sampled signals when the clock signal is at a second voltage level;
detect a voltage level of a first one of the sampled signals by a first threshold adjusted inverter, wherein a threshold voltage of the first threshold adjusted inverter is entirely outside of a transition voltage range of the sampler circuit;
detect a voltage level of a second one of the sampled signals by a second threshold adjusted inverter, wherein a threshold voltage of the second threshold adjusted inverter is entirely outside of the transition voltage range of the sampler circuit; and
combining the detected voltage levels of the first and second sampled signals to transition an output signal from the first level to the second level in response to one of the detected voltage levels of the first and second sampled signals transitioning from the second voltage level to the first voltage level; and
a feedback circuit configured to receive the output signal and generate the clock signal.
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Abstract
A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.
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Citations
20 Claims
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1. A self-clocked sampler system, comprising:
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a sampler circuit configured to sample input signals when a clock signal is at a first level to produce sampled signals; a detection circuit that is coupled to the sampler circuit and configured to; pre-charge the sampled signals when the clock signal is at a second voltage level; detect a voltage level of a first one of the sampled signals by a first threshold adjusted inverter, wherein a threshold voltage of the first threshold adjusted inverter is entirely outside of a transition voltage range of the sampler circuit; detect a voltage level of a second one of the sampled signals by a second threshold adjusted inverter, wherein a threshold voltage of the second threshold adjusted inverter is entirely outside of the transition voltage range of the sampler circuit; and combining the detected voltage levels of the first and second sampled signals to transition an output signal from the first level to the second level in response to one of the detected voltage levels of the first and second sampled signals transitioning from the second voltage level to the first voltage level; and a feedback circuit configured to receive the output signal and generate the clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A computer-implemented method, comprising:
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pre-charging sampled signals, by a detection circuit, when a clock signal is at a second voltage level; sampling input signals, by a sampler circuit, when the clock signal is at a first voltage level to drive the sampled signals; detecting a voltage level of a first one of the sampled signals by a first threshold adjusted inverter, wherein a threshold voltage of the first threshold adjusted inverter is entirely outside of a transition voltage range of the sampler circuit; detecting a voltage level of a second one of the sampled signals by a second threshold adjusted inverter, wherein a threshold voltage of the second threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit; combining, by the detection circuit, the detected voltage levels of the first and second sampled signals to transition an output signal from the first voltage level to the second voltage level in response to one of the detected voltage levels of the first and second sampled signals transitioning from the second voltage level to the first voltage level; and generating the clock signal by a feedback circuit that receives the output signal. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification