CMOS-MEMS INTEGRATION WITH THROUGH-CHIP VIA PROCESS

• US 20200131028A1
• Filed: 05/23/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Chun-Wen, Chu, Chia-Hua, Kuo, Wen Cheng, Mao, Wei-Jhih
• Granted Patent: US 11,235,969 B2
• Time in Patent Office: Days
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 2207/095 through the lid
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/036 Fusion bonding
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: B81C 3/001 Bonding of two components

Abstract

The integrated CMOS-MEMS device includes a CMOS structure, a cap structure, and a MEMS structure. The CMOS structure, fabricated on a first substrate, includes at least one conducting layer. The cap structure, including vias passing through the cap structure, has an isolation layer deposited on its first side and has a conductive routing layer deposited on its second side. The MEMS structure is deposited between the first substrate and the cap structure. The integrated CMOS-MEMS device also includes a conductive connector that passes through one of the vias and through an opening in the isolation layer on the cap structure. The conductive connector conductively connects a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.

Claims

1. An apparatus comprising:

a CMOS structure, fabricated on a first substrate, including at least one CMOS device and at least one conducting layer;

a cap structure, including vias passing through the cap structure, having an isolation layer deposited on a first side thereof and having a conductive routing layer deposited on a second side thereof;

a MEMS structure, deposited between the first substrate and the cap structure, including at least one MEMS device; and

a conductive connector, passing through one of the vias and through an opening in the isolation layer on the cap structure, and conductively connecting a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.

2. The apparatus of claim 1, wherein the at least one conducting layer is a top metal layer of the CMOS structure.

3. The apparatus of claim 1, wherein the one of the vias that the conductive connector passes through is coated with isolating material on its inner surface.

4. The apparatus of claim 1, wherein the MEMS structure is deposited between the CMOS structure and the cap structure, and wherein the conductive connector comprises:

a conducting pad, deposited on a surface of the MEMS structure that faces the isolation layer on the cap structure, and conductively connecting to the at least one conducting layer of the CMOS structure; and

a conductive contact, passing through the one of the vias and through the opening in the isolation layer on the cap structure, and conductively connecting the conductive path in the conductive routing layer with the conducting pad.

5. The apparatus of claim 1, wherein the MEMS structure is fabricated in a MEMS wafer located between the first substrate and the cap structure, and wherein the conductive connector comprises:

a silicon plug, passing through the MEMS wafer and extending into the isolation layer on the cap structure, and conductively connecting to the at least one conducting layer of the CMOS structure; and

a conductive contact, passing through the one of the vias and through the opening in the isolation layer on the cap structure, and conductively connecting the conductive path in the conductive routing layer with the silicon plug.

6. The apparatus of claim 1, wherein both the MEMS structure and the CMOS structure are fabricated on the first substrate, and wherein the conductive connector comprises:

a conductive contact, passing through the one of the vias and through the opening in the isolation layer on the cap structure, and conductively connecting to the at least one conducting layer of the CMOS structure.

7. The apparatus of claim 1, wherein both the MEMS structure and the CMOS structure are fabricated on the first substrate, and wherein the conductive connector comprises:

a silicon pillar, fabricated in the cap structure and surrounded by a trench ring on the first side of the cap structure, and conductively connecting to the at least one conducting layer of the CMOS structure; and

a conductive contact, passing through the one of the vias and through the opening in the isolation layer on the cap structure, and conductively connecting the conductive path in the conductive routing layer with the silicon pillar.

8. The apparatus of claim 7, wherein the trench ring is filled at least partially with isolation material.

9. A method comprising:

fabricating a CMOS-MEMS structure that includes a CMOS structure and a MEMS structure, wherein the CMOS structure includes at least one CMOS device and at least one conducting layer;

fabricating a cap structure by etching a first side of a cap wafer to form one or more cavities, with an isolation layer formed on the first side of the cap wafer;

bonding the cap structure to the CMOS-MEMS structure;

etching one or more trenches at a second side of the cap wafer; and

depositing conductive material towards the second side of the cap wafer and surfaces of the one or more trenches, to form a conductive contact that passes through one of the trenches at the second side of the cap wafer and conductively connected to the at least one conducting layer of the CMOS structure.

10. The method of claim 9, comprising:

fabricating the CMOS structure on a first substrate; and

forming the MEMS structure at a location between the first substrate and the cap structure.

11. The method of claim 10, comprising:

forming a conducting pad on a surface of the MEMS structure that faces the isolation layer on the cap structure, with the conducting pad conductively connected to the at least one conducting layer of the CMOS structure; and

wherein the conductive contact is conductively connected to the conducting pad through the one of the trenches at the second side of the cap wafer and through an opening in the isolation layer on the first side of the cap wafer.

12. The method of claim 9, wherein both the MEMS structure and the CMOS structure are fabricated on a first substrate, and wherein the bonding the cap structure comprises:

bonding the cap structure to the CMOS-MEMS structure with hybrid bonding.

13. The method of claim 12, comprising:

conductively connecting the conductive contact with the at least one conducting layer of the CMOS structure when depositing the conductive material towards the second side of the cap wafer and the surfaces of the one or more trenches.

14. The method of claim 12, comprising:

fabricating at least one trench ring on the first side of the cap wafer to form a silicon pillar surrounded by the at least one trench ring; and

forming the isolation layer on the first side of the cap wafer and an isolation coating on an inner surface of the at least one trench ring.

15. The method of claim 14, comprising:

conductively connecting the silicon pillar with the at least one conducting layer of the CMOS structure when bonding the cap wafer to the CMOS-MEMS structure; and

conductively connecting the conductive contact with the silicon pillar when depositing the conductive material towards the second side of the cap wafer and the surfaces of the one or more trenches.

16. The method of claim 9, further comprising:

depositing isolation material onto the second side of the cap wafer and the surfaces of the one or more trenches before depositing conductive material.

17. The method of claim 9, wherein depositing the conductive material comprises:

depositing the conductive material onto isolation material that is located on the second side of the cap wafer and on the surfaces of the one or more trenches.

18. The method of claim 9, further comprising:

depositing passivation layer on the conductive material at the second side of the cap wafer and the surfaces of the one or more trenches at the second side of the cap wafer.

19. A method comprising:

fabricating, on a first substrate, a CMOS structure that includes at least one CMOS device and at least one conducting layer;

fabricating a cap structure on a cap wafer, wherein the fabricating the cap structure includes etching a first side of the cap wafer to form one or more cavities, with an isolation layer deposited on the first side of the cap wafer;

bonding the cap structure to a MEMS wafer;

forming at least one silicon plug extending at least through the MEMS wafer that has a first side thereof bonded to the isolation layer on the first side of the cap wafer;

eutectic bonding the MEMS wafer to the first substrate;

etching one or more trenches at a second side of the cap wafer; and

depositing conductive material towards the second side of the cap wafer and inner surfaces of the one or more trenches, to form a conductive contact that passes through one of the trenches at the second side of the cap wafer and conductively connected to the at least one silicon plug.

20. The method of claim 19, comprising:

fabricating, in the MEMS wafer, a MEMS structure that includes at least one MEMS device.