METHODS AND APPARATUS FOR CONTROLLING WARPAGE IN WAFER LEVEL PACKAGING PROCESSES

• US 20200131624A1
• Filed: 09/26/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: LIANTO, PRAYUDI, RAFI, MOHAMED, SULAIMAN, MUHAMMAD AZIM BIN SYED, SEE, GUAN HUEI, KRISTY, ANG YU XIN, ELUMALAI, KARTHIK, THIRUNAVUKARASU, SRISKANTHARAJAH, SUNDARRAJAN, ARVIND
• Granted Patent: US 11,421,316 B2
• Time in Patent Office: Days
• CPC Class Codes: C23C 14/541 Heating or cooling of the substrates
• CPC Class Codes: H01L 21/67109 mainly by convection
• CPC Class Codes: H01L 21/67115 mainly by radiation
• CPC Class Codes: H01L 21/67248 Temperature monitoring
• CPC Class Codes: H01L 21/67288 Monitoring of warpage, curvature, damage, defects or the like
• CPC Class Codes: H01L 2224/0233 Structure of the redistribution layers
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/3511 Warping

Abstract

Methods and apparatus for producing fine pitch patterning on a substrate. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2/2 μm l/s fine pitch patterning.

Claims

1. A method of fine pitch patterning on a substrate in a wafer level packaging process, comprising:

performing a first warpage correction process on the substrate by ramping to and holding the substrate at a first temperature for a first duration and ramping to and holding a second temperature for a second duration, wherein the first temperature is greater than the second temperature;

forming vias in a polymer layer on the substrate;

curing the polymer layer;

performing a second warpage correction process on the substrate by ramping to and holding the substrate at a third temperature for a third duration and ramping to and holding the substrate at a fourth temperature for a fourth duration, wherein the third temperature is greater than the fourth temperature; and

forming a redistribution layer on the substrate with a fine pitch patterning having a line/space of 10/10 μ

m or less.

2. The method of claim 1, wherein the fine pitch patterning has a line/space of 5/5 μ

m or less.

3. The method of claim 1, wherein the fine pitch patterning has a line/space of 2/2 μ

m or less.

4. The method of claim 1, wherein the substrate has a warpage of 500 μ

m or less after the second warpage correction process.

5. The method of claim 4, wherein the substrate has a warpage of 400 μ

m or less after the second warpage correction process.

6. The method of claim 1, wherein the first temperature of the first warpage correction process is greater than the third temperature of the second warpage correction process.

7. The method of claim 1, wherein the first temperature of the first warpage correction process is approximately equal to the third temperature of the second warpage correction process.

8. The method of claim 1, wherein a subsequent first temperature of a subsequent first warpage correction process is based on the first temperature of the first warpage correction process.

9. The method of claim 1, wherein the first temperature is approximately a glass transition temperature of the polymer layer on the substrate.

10. The method of claim 1, wherein the first temperature, the second temperature, the third temperature, or the fourth temperature is obtained by ramping linearly.

11. The method of claim 1, wherein the first temperature is lower than a glass transition temperature of the polymer layer when a plasma vapor deposition (PVD) process has been performed prior to the first warpage correction process.

12. The method of claim 1, wherein the substrate is a reconstituted wafer composed of multiple dies.

13. The method of claim 1, further comprising:

performing a chemical mechanical polishing (CMP) process to enhance the fine pitch patterning.

14. A method of fine pitch patterning on a substrate in a wafer level packaging process, comprising:

determining material composition, thickness, or prior processing of the substrate;

heating the substrate to a first temperature over a first time period based on the material composition, thickness, or prior processing of the substrate;

maintaining the substrate at the first temperature for a second time period; and

cooling the substrate to a second temperature over a second time period based on the material composition, thickness, or prior processing of the substrate.

15. The method of claim 14, wherein the first temperature is approximately 150 degrees Celsius to 220 degrees Celsius.

16. The method of claim 14, wherein the first temperature is reduced when a prior processing of the substrate includes a physical vapor deposition (PVD) process.

17. The method of claim 14, wherein the first temperature is above a glass transition temperature of a material of the substrate.

18. The method of claim 14, wherein the first temperature is approximately 175 degrees Celsius.

19. A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method of fine pitch patterning on a substrate in a wafer level packaging process to be performed, the method comprising:

performing a first warpage correction process on the substrate by ramping to and holding the substrate at a first temperature for a first duration and ramping to and holding a second temperature for a second duration, wherein the first temperature is greater than the second temperature;

forming vias in a polymer layer on the substrate;

curing the polymer layer;

performing a second warpage correction process on the substrate by ramping to and holding the substrate at a third temperature for a third duration and ramping to and holding the substrate at a fourth temperature for a fourth duration, wherein the third temperature is greater than the fourth temperature; and

forming a redistribution layer on the substrate with a fine pitch patterning having a line/space of 10/10 μ

m or less.

20. The non-transitory, computer readable medium of claim 19, wherein the first temperature of the first warpage correction process is greater than the third temperature of the second warpage correction process, wherein the substrate has a warpage of 400 μ

m or less after the second warpage correction process, and wherein the fine pitch patterning has a line/space is 2/2 μ

m or less.