Wafer Alignment Mark Scheme

• US 20200132436A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 03/28/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tseng, Wei-Hsiang, Lin, Chin-Hsiang, Liu, Heng-Hsin, Peng, Jui-Chun, Chen, Ho-Ping
• Granted Patent: US 11,162,777 B2
• Time in Patent Office: Days
• CPC Class Codes: G01B 11/02 for measuring length, width or thickness G01B11/08 takes precedence
• CPC Class Codes: G03F 9/7011 Pre-exposure scan; original with original holder alignment; Prealignment, i.e. workpiece with workpiece holder
• CPC Class Codes: G03F 9/7084 Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.

Claims

1. A semiconductor device comprising:

a semiconductor wafer comprising a first side and a second side opposite the first side;

active devices located adjacent to the first side;

a first alignment mark in the second side, the first alignment mark comprising first recesses, wherein the first recesses change a light intensity reflected from the semiconductor wafer a first amount; and

a second alignment mark in the second side, the second alignment mark comprising second recesses, the second recesses being identifiably different from the first recesses, wherein the second recesses change a light intensity reflected from the semiconductor wafer a second amount identifiably different from the first amount.

2. The semiconductor device of claim 1, wherein the second alignment mark is located 90°

away from the first alignment mark.

3. The semiconductor device of claim 1, wherein the second alignment mark is located 120°

away from the first alignment mark.

4. The semiconductor device of claim 1, further comprising a third alignment mark comprising third recesses, the third recesses being identifiably different from the first recesses and the second recesses.

5. The semiconductor device of claim 4, further comprising a fourth alignment mark comprising fourth recesses, the fourth recesses being identifiably different from the first alignment mark, the second alignment mark, and the third alignment mark.

6. The semiconductor device of claim 5, where each one of the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark are located equally away from each other.

7. The semiconductor device of claim 1, wherein the first alignment mark has a pyramidal shape.

8. A semiconductor device comprising:

a semiconductor wafer;

a first set of recesses within the semiconductor wafer, wherein each recess within the first set of recesses is aligned with other recesses within the first set of recesses; and

a second set of recesses within the semiconductor wafer, the second set of recesses having a different number of recesses from the first set of recesses, wherein each recess within the second set of recesses is aligned with other recesses within the second set of recesses.

9. The semiconductor device of claim 8, wherein each recess within the first set of recesses is filled with a dielectric material.

10. The semiconductor device of claim 8, wherein the first set of recesses is located 90°

away from the second set of recesses.

11. The semiconductor device of claim 8, wherein the first set of recesses has a pyramidal shape.

12. The semiconductor device of claim 8, wherein the first set of recesses is located 120°

away from the second set of recesses.

13. The semiconductor device of claim 8, wherein the first set of recesses has a square shape.

14. The semiconductor device of claim 8, wherein the first set of recesses has a first depth of about 0.12 μ

m.

15. A semiconductor device comprising:

a semiconductor wafer with a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant;

a first alignment mark located within the first quadrant;

a second alignment mark located within the second quadrant;

a third alignment mark located within the third quadrant; and

a fourth alignment mark located within the fourth quadrant, wherein reflected light is identifiably different based on which of the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark reflects the reflected light.

16. The semiconductor device of claim 15, wherein the first alignment mark has a first depth of about 0.12 μ

m.

17. The semiconductor device of claim 15, wherein the first alignment mark has a first depth of between about 100 nm and about 200 nm.

18. The semiconductor device of claim 15, wherein the first alignment mark has a rectangular shape.

19. The semiconductor device of claim 15, wherein the first alignment mark is located 90°

away from the second alignment mark.

20. The semiconductor device of claim 15, wherein the first alignment mark comprises a plurality of circular holes.