1. An integrated circuit (IC), comprising:
- a flexible plate comprising a first pair of arms and a second pair of arms, the first pair orthogonal to the second pair;
piezoelectric capacitors on each of respective arms of the first pair and on each of the arms of the second pair; and
a proof mass coupled to the flexible plate and offset from the first and second pair of arms.
An acceleration change sensor includes a flexible member comprising extensions extending from a central portion. Piezoelectric capacitors are provided on respective extensions. A proof mass is coupled to the flexible member and offset from each extension of the plurality of extensions.
- 1. An integrated circuit (IC), comprising:
a flexible plate comprising a first pair of arms and a second pair of arms, the first pair orthogonal to the second pair; piezoelectric capacitors on each of respective arms of the first pair and on each of the arms of the second pair; and a proof mass coupled to the flexible plate and offset from the first and second pair of arms.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- 10. An acceleration change sensor, comprising:
a flexible member comprising first and second extensions extending from a central portion; piezoelectric capacitors on each of the first and second extensions of the plurality of extensions; and a proof mass coupled to the flexible member and offset from each of the first and second extensions.
- View Dependent Claims (11, 12, 13, 14, 15, 16)
- 17. An integrated circuit (IC), comprising:
piezoelectric capacitors on each of the arms of the first pair and on each of the arms of the second pair; a proof mass coupled to the flexible plate and offset from the first and second pair of arms, the proof mass at least partially residing within a cavity; and a cap on a side of the flexible plate opposite the proof mass; wherein the piezoelectric capacitors are configured to be subject to strain upon movement of the proof mass within the cavity.
- View Dependent Claims (18, 19, 20)
This application claims priority to U.S. Provisional Application No. 62/752,459, filed Oct. 30, 2018, which is hereby incorporated by reference.
Shock sensors are accelerometers that detect change in acceleration with time. Many types of shock sensors are stand-alone devices that are connected to circuitry external to the sensor. Many shock sensors comprise single-axis accelerometers meaning that they are sensitive to acceleration in only one axis.
In one example, an integrated circuit (IC) includes a flexible plate, piezoelectric capacitors, and a proof mass. The flexible plate includes a first pair of arms and a second pair of arms. The first pair of arms is orthogonal to the second pair of arms. The piezoelectric capacitors are on each of the arms of the first pair and on each of the arms of the second pair. The proof mass is coupled to the flexible plate and offset from the first and second pair of arms.
The accelerometer change sensor described herein comprises a three-axis piezoelectric sensor. The sensor can be integrated on to a semiconductor die with the circuitry that drives the sensor and processes its output signals. The sensor can be fabricated using micro-electrical mechanical system (MEMS) and wafer level processing to produce a semiconductor device with analog and digital circuitry integrated on the same die as the piezoelectric sensor.
The ends of the arms at which the piezoelectric capacitors are formed do not move as the proof mass 120 moves. That is, end 131 of arm 112 remains stationary as force is applied on the opposite end 141 of the arm. Similarly, ends 132, 133, and 134 of arms 113, 114, and 115 remain stationary as the proof mass moves.
The arms 112-115 in
As the piezoelectric sensor 100 is subjected to acceleration, the proof mass 120 will move up and down and/or tilt back and forth relative to the arms.
Cap 550 is formed over the arms of the flexible plate 110 to protect the sensor from external contaminants and damage. Cap 550 may be formed via wafer scale processing as a separate wafer attached to the wafer containing the flexible plate 110 and then etched to form caps 550. Cap 550 and substrate 540 also provide a mechanical stop to prevent excessive vertical excursion (in direction of arrow 121) of the flexible plate 110. Excessive acceleration that would otherwise cause the central portion 220 to flex to the point that it would break is prevented from reaching that level of flexure as either the proof mass 120 will contact surface 541 of substrate 540 or the central portion of the flexible plate 110 will contact surface 551 of the cap 550.
The arms of the flexible plate experience strain due to movement of the proof mass.
In the examples of
As made, the polarization of the domains of the piezoelectric capacitors 122-125 are generally oriented in random directions, which if used as such will result in a relatively small output signal when subject to strain. Before using a piezoelectric as shock sensor, the piezoelectric domains are poled, which involves the application of a voltage across electrodes of the piezoelectric in an attempt to align a larger percentage of the domains in the same direction thereby resulting in a larger signal-to-noise ratio.
Precondition circuit 720 includes an initialization finite state machine (INIT FSM) 722 in any suitable form, such as comprising logic gates, a controller, and the like. INIT FSM 722 achieves state transitions or sequential operations, as detailed later in connection with communicating n+1 poling signals S0 through Sn ultimately to the piezo capacitor stack 730. In the example shown in
Piezo capacitor stack 730 includes a number n of serially-connected capacitors, indicated C0 through Cn−1, referred to as a stack to connote the serial connection between successive capacitors, that is, an upper electrode of capacitor C0 is connected to a lower electrode of capacitor C1, an upper electrode of capacitor C1 is connected to a lower electrode of capacitor C2, and so forth up through an upper electrode of capacitor Cn−2 being connected to a lower electrode of capacitor Cn−1. The value of n may be, for example, one or more, and in some instance is in the range of 3 to 64. For connecting poling signals and as described later, the number n of capacitors Cx is one less than the number of buffers Bx (and low leakage switches LLSx).
Concluding the connectivity of the capacitor stack 730, the lower electrode of capacitor C0 is connected (in addition to switch LLS0 described above) through a lower stack switch SLS to a reference voltage VREF. The upper electrode of capacitor Cn−1 is connected (in addition to switch LLSn described above) through an upper stack switch SUS to an output 730out to a corresponding amplifier 742. The stack switches SLS and SUS are controlled by a corresponding
Sensor output circuit 740 includes a differential amplifier 742. The inverting input of each amplifier 742 is connected to the output 730out of the capacitor stack 730. The non-inverting input of amplifier 742 is connected to VREF, which is connected to the lower electrode of capacitor C0 in each capacitor stack. A feedback capacitor CFB is connected between the output and inverting input of each amplifier 742. The ratio between the sensor stack capacitance and capacitor CFB is essentially a capacitive voltage divider and determines the amplifier gain.
A reset switch, SRES, is connected in parallel with feedback capacitor CFB, whereby switch SRES is operable to close in response to a signal AMP_RST for purposes of defining a direct current (DC) bias point by asserting AMP_RST, initializing 730out, and then de-asserting AMP_RST after which alternating current (AC) voltage is properly divided as between CFB and the capacitor stack 730. In this regard, therefore, switch SRES allows for compensation in that the amplifier 742 does not have resistive feedback, so any charge accumulation across capacitor CFB (due to leakage of any source) can cause the amplifier'"'"'s output voltage to drift. Accordingly, AMP_RST can be asserted: (i) before sensing mode starts; (ii) periodically to mitigate drift; or (iii) when large vout offset is observed, where the last two scenarios also apply to temperature changes.
The piezo capacitor stack 730 is poled from time-to-time (e.g., at system start-up, at fixed time intervals during operation of the sensor 100, etc.).
After initializing the index value, at 804 a first subset of poling signals S0 through Sn, namely, S0 to Sx, are set to VDD, while a second subset of poling signals, namely, the remaining Sx+1 to Sn, are set to ground (shown as zero volts). By way of example, therefore, for the first iteration of operation 804 (i.e., x=0 from operation 802), then the first subset of signals has S0=VDD, while the second and remaining poling signals S1 through Sn all equal 0. To further illustrate this example,
Referring back to
At 806 in
For each increase in loop index x in
For each successive loop iteration x of method 800, one additional capacitor at a time (e.g., per CLK of INIT FSM 722 of
As described above, method 800 commences with 0 volts across each capacitor in the capacitor stack, and then from a direction in ascending index x for capacitor Cx in the capacitors C0 up to Cn−1, then one capacitor a time and for that index is biased to a first polarity having a first magnitude and a first direction, and then in a successive ascension of the index to x+1 that same capacitor is further biased to maintain that same first polarity direction, albeit changing, potentially, by some difference in magnitude. Given that the sequence of such changing biases may be perceived as from the bottom of the stack (i.e., as to capacitor C0, closest to VREF), in an upward direction in the schematic sense of stack 730 (i.e., toward capacitor Cn−1, the top electrode of which is the stack output vout), then the process may be perceived as akin to an upward zipper of values, where each ascendant step of the zipper is the new application of VDD to a next selected capacitor upper electrode in the serial chain, thereby moving that capacitor to a negative polarity while ensuring the capacitor(s) below the selected capacitor also maintain(s) a likewise, and earlier established, negative polarity. Accordingly, as the figurative zipper moves up, the magnitude of the polarization across each capacitor may recede, but it will not change state (i.e., from negative to positive or vice versa) by virtue of the sequencing of the preferred embodiment. As a result, upon completion of method 500, all capacitors in the stack have co-aligned directionality of polarization.
Having described a bottom-upward, negative polarization technique for capacitor stack 730, an embodiment also includes a defined sequence to prevent random events, such as the possibility of a change in polarity direction, while removing the non-zero biases applied by poling signals S0 through Sn to the capacitor stack. In this regard,
Method 1100 commences at 1102, in which the loop index x is initialized to n, that is, the number of the topmost poling signal Sn, again to facilitate a sequential looping through a total of n+1 iterations for the n+1 poling signals, but here in a decrementing fashion so as to sequence from the top of capacitor stack 730 downward. Meanwhile, again for operation 1102 (as was the case for method 800 of
At 1104, a first subset of the poling signals S0 through Sn, namely, S0 to Sx−1, are set to VDD (or maintained at VDD from method 800) while a second subset of the poling signals Sx through Sn, being the remaining poling signals not included in the first subset and, therefore, Sx to Sn, are set to ground (shown as zero volts). By way of example, therefore, for the first iteration of 1104 (i.e., x=n from step 1102), then the first subset of signals has S0 through Sn−1 equal to VDD, while the second subset and remaining poling signal Sn equals 0. To further illustrate this example,
Method 1100 continues to at operation 1106, which compares the loop index x to see if it has reached zero, that is, in effect determining whether the bottommost poling signals Sn has been processed in the loop. If the loop index x is greater than zero, then method 1100 proceeds to operation 1108 which decrements the loop index x and returns flow to step 1104, whereas if the loop index x reaches (i.e., is equal to) zero, then method 1100 proceeds to operation 1110 in which EN is set to zero so as to complete the method and whereby its complement thereby closes switches SUS and SLS.
For each decrease in loop index x, then from the top of the capacitor stack downward, each successive capacitor Cx will receive a voltage of 0 at its upper electrode, with a voltage of VDD at its lower electrode, thereby causing the capacitor, in response to those respective voltages, and the −VDD difference between them, to achieve a polarization of −P1.
From the above, method 800 essentially achieves a uniform negative polarization of −P2 across each capacitor in the capacitor stack 730 (see
Referring again to
The material used for the piezoelectric capacitors may comprise lead zirconate titanate (PZT) which may have a substantial pyroelectric property. A pyroelectric property means that the material is sensitive to changes in temperature. As, such the piezoelectric sensor 100 may not be able to differentiate changes in temperature from changes in mechanical strain.
Reference capacitors 1352, 1353, 1354, and 1355 are shown near respective piezoelectric capacitors 1322-1325. Reference capacitors 1352-1355 may be made from the same material as piezoelectric capacitors 1322-1325 (e.g., lead zirconate titanate). As such, the effect of temperature on piezoelectric capacitors 1323-1325 (which sense strain) is the same as on the reference capacitors 1352-1355. Although formed on the same layer of material (e.g., silicon dioxide) comprising flexible plate 1310, reference capacitors 1352-1355 are mechanically isolated from capacitors 1322-1325 by etching the silicon dioxide between the sets of capacitors. Reference capacitor 1352 is mechanically from corresponding piezoelectric capacitor 1322 by trench 1342 etched through the silicon dioxide layer. Similarly, reference capacitor 1353 is mechanically isolated from corresponding piezoelectric capacitor 1323 by trench 1343. Reference capacitor 1354 is mechanically from corresponding piezoelectric capacitor 1324 by trench 1344, and reference capacitor 1355 is mechanically from corresponding piezoelectric capacitor 1325 by trench 1345. As such, reference capacitors 1352-1355 are not subjected to the strain to which the piezoelectric capacitors 1322-1325 are subjected by movement of the proof mass 1320. The reference capacitors 1352-1355 have the same temperature coefficient as the main sense piezoelectric capacitors 1323-1325 but are mechanically isolated form the piezoelectric capacitors.
The effect of temperature can be removed from the X, Y, and Z acceleration signals as follows. Accelerations in the X and Y directions, respectively, are calculated as X=X′−RX′−X+RX″ and Y=Y′−RY′−Y″−RY″, where RX′ is the signal from the reference capacitor 1352, RX″ is the signal from the reference capacitor 1353, RY′ is the signal from the reference capacitor 1354, and RY″ is the signal from the reference capacitor 1355. Since the temperature changes of X′ and X″ are the same and the temperature changes of Y′ and Y″ are the same, the acceleration change can be calculated for the X direction as X=X′−X″ and Y=Y′−Y″ without using signals from the reference capacitors. The acceleration in the Z direction is determined as the sum of the four X and Y signals minus the sum of the corresponding reference capacitor signals, that is, Z=X′+X″+Y′+Y′−′RX′−RX″−RY′−RY′. The reference capacitors are useful for the determination of the Z direction acceleration change because the sense capacitors X′, X″, Y′, and Y″ are all added or combined. The reference capacitors are needed to provide the temperature compensation.
The outputs of the voltage amplifiers 1409-1412 are coupled together (to thereby add together the signals from the reference capacitors 1352-1355) and to an input of current amplifier 1422. Similarly, the outputs of the voltage amplifiers 1405-1408 are coupled together (to thereby add together the signals from the main sense piezoelectric capacitors 1322-1325) and to another input of current amplifier 1422, to thereby generate the Az signal.
The outputs of voltage amplifiers 1401 (which provides the X′ signal) and 1402 (which provides the X″ signal) are coupled to respective inputs of current amplifier 1420 to thereby generate the Ax signal (X′-X″). Similarly, the outputs of voltage amplifiers 1403 (which provides the Y′ signal) and 1404 (which provides the Y″ signal) are coupled to respective inputs of current amplifier 1421 to thereby generate the Ay signal (Y′-Y″).
In this description, the term “couple” or “couples” means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.