DIGITAL TIME-DOMAIN READOUT CIRCUIT FOR BIOFET SENSORS

• US 20200132621A1
• Filed: 12/31/2019
• Published: 04/30/2020
• Est. Priority Date: 07/27/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HUANG, Yu-Jie, HUANG, Jui-Cheng
• Granted Patent: US 11,243,184 B2
• Time in Patent Office: Days
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82

Abstract

Various bioFET sensor readout circuits and their methods of operation are described. A readout circuit includes a plurality of logic gates coupled in cascade, a delay extractor, and a counting module. Each logic gate of the plurality of logic gates includes at least one bioFET sensor. The delay extractor is designed to generate a pulse-width signal based on a time difference between an output signal from the plurality of logic gates and a reference signal. The counting module is designed to receive the pulse-width signal and output a digital count corresponding to a width of the pulse-width signal.

Claims

1. A method comprising:

generating a sensor signal using a first set of logic gates having bioFET sensors;

determining a time difference between an output signal from the first set of logic gates and a reference signal using a delay extractor;

generating a pulse-width signal using the delay extractor based on the time difference; and

determining a digital count based on a width of the pulse-width signal using a counting module.

2. The method of claim 1, further comprising coupling the first set of logic gates in a cascade configuration.

3. The method of claim 1, further comprising generating the reference signal using a second set of logic gates that are coupled in a cascade configuration.

4. The method of claim 3, wherein the determining the time difference comprises providing a same input signal to the first and second set of logic gates.

5. The method of claim 1, further comprising forming each of the logic gates of the first set of logic gates with inverters.

6. The method of claim 1, wherein the generating the pulse-width signal comprises using an XOR logic gate of the delay extractor.

7. The method of claim 1, wherein the determining the digital count comprises:

receiving the pulse-width signal and a clock signal using an AND gate of the counting module; and

generating a pulse count signal based on the pulse-width signal and the clock signal.

8. The method of claim 1, wherein the determining the digital count comprises:

generating a pulse count signal using an AND gate of the counting module based on the pulse-width signal; and

generating the digital count using a digital counter of the counting module based on the pulse count signal.

9. The method of claim 1, further comprising forming the bioFET sensor in each of the first set of logic gates with a dual-gate bioFET sensor.

10. The method of claim 1, further comprising:

functionalizing the bioFET sensor in each of the first set of logic gates with a first capture reagent;

functionalizing a transistor in each of a second set of logic gates with a second capture reagent that is different from the first capture reagent;

generating the reference signal using the second set of logic gates that are coupled in a cascade configuration.

12. The method of claim 10, wherein the generating the oscillating output signal comprises feeding back an output of the plurality of inverters as an input to the plurality of inverters using a feedback line.

13. The method of claim 10, wherein the determining the digital count comprises:

receiving the oscillating output signal and a clock signal using an AND gate of the counting module; and

generating a pulse count signal based on the oscillating output signal and the clock signal.

14. The method of claim 10, wherein the determining the digital count comprises:

generating a pulse count signal using an AND gate of the counting module based on the oscillating output signal; and

generating the digital count using a digital counter of the counting module based on the pulse count signal.

15. The method of claim 10, wherein the frequency of the oscillating output signal is between 150 MHz and 250 MHz.

16. The method of claim 10, further comprising forming the bioFET sensor in each of the plurality of inverters with a dual-gate bioFET sensor.

11. A method comprising:

generating a sensor signal using a plurality of inverters coupled in a cascade configuration, wherein each inverter of the plurality of inventers is formed with at least one bioFET sensor;

generating an oscillating output signal using the plurality of inverters; and

determining a digital count using a counting module based on a frequency of the oscillating output signal.

17. A method comprising:

generating a sensor signal using a first set of logic gates coupled in a cascade configuration, wherein each logic gate of the first of logic gate is formed with at least one bioFET sensor;

generating an oscillating output signal using the first set of logic gates;

generating a mixed signal using a mixer based on a reference oscillating signal received from a second set of logic gates and the oscillating output signal; and

determining a digital count using a counting module based on a frequency of the mixed signal.

18. The method of claim 17, wherein the generating the mixed signal comprises generating a down-converted signal corresponding to a difference in an oscillation frequency between the oscillating output signal and the reference oscillating signal.

19. The method of claim 17, wherein the generating the oscillating output signal comprises feeding back an output of the first set of logic gates as an input to the first set of logic gates using a feedback line.

20. The method of claim 17, wherein the determining the digital count comprises:

receiving the mixed signal and a clock signal using an AND gate of the counting module;

generating a pulse count signal based on the mixed output signal and the clock signal; and

generating the digital count using a digital counter of the counting module based on the pulse count signal.