SYSTEM AND METHOD TO SECURE FPGA CARD DEBUG PORTS

• US 20200132761A1
• Filed: 10/25/2018
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Rahardjo, Johan, Gavvala, Pavan Kumar
• Granted Patent: US 10,852,352 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 21/305 by remotely controlling device operation
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices

Abstract

Embodiments are described for securing access to a debug port of an FPGA (Field Programmable Gate Array) card installed within an IHS (Information Handling System). A remote access controller determines the status of the FPGA card debug port via a query to a management controller of the FPGA card. The remote access controller generates a passcode for the debug port and disables the debug port via a message to the management controller. The management controller detects a request, that includes a requestor password, for access to the debug port. The remote access controller authorizes the requestor'"'"'s access to the debug port if the requestor password matches the generated passcode. The remote access controller disables the debug port upon each power cycle of the FPGA card or upon detecting removal of a device from the debug port.

Claims

1. A method for securing access to an FPGA (Field Programmable Gate Array) card debug port by a remote access controller, the method comprising:

determining a status of the FPGA card debug port via a query to a management controller of the FPGA card;

generating a passcode for the debug port;

disabling the debug port via a message to the management controller;

detecting a request for access to the debug port by a requestor, wherein the request includes a requestor password;

providing the requestor access to the debug port, if the requestor password matches the generated passcode; and

disabling the debug port upon the next power cycle of the FPGA card.

2. The method of claim 1, wherein the management controller communicates with a service processor of the remote access controller via a sideband management bus.

3. The method of claim 2, wherein the service processor limits access to the generated passcode to authenticated administrators with access to the remote access controller.

4. The method of claim 1, wherein the passcode is generated by hashing a serial number of the FPGA card concatenated with a service tag of the IHS (Information Handling System) in which the FPGA card is installed.

5. The method of claim 1, wherein the passcode is generated based on inputs provided via a user interface of the remote access controller.

6. The method of claim 1, wherein, upon enabling of the debug port, the debug port is disabled upon detecting de-coupling of a device from the debug port.

7. The method of claim 6, wherein the management controller detects the de-coupling of the device from the debug port and reports the disabling of the debug port to the remote access controller.

14. The system of claim 6, wherein the management controller detects the de-coupling of the device from the debug port and reports the disabling of the debug port to the remote access controller.

8. A system for securing access to a debug port of an FPGA (Field Programmable Gate Array) card installed in an Information Handling System (IHS), the system comprising:

a remote access controller configured to monitor operations of the IHS, the remote access controller configured to;

issue a query to a management controller of the FPGA card to determine a status of the FPGA card debug port;

generate a passcode for the debug port;

disable the debug port via a message to the management controller;

receive a request for access to the debug port, wherein the request includes a requestor password;

authorize access to the debug port by the requestor, if the requestor password matches the generated passcode; and

disable the debug port upon the next power cycle of the FPGA card; and

the management controller configured to;

determine the status of the debug port in response to the query from the remote access controller;

detect the coupling of a device to the debug port;

receive a request from the device for the requestor to access the debug port, wherein the request includes the requestor password; and

enable the debug port upon the authorization of the remote access controller.

9. The system of claim 8, wherein the management controller communicates with a service processor of the remote access controller via a sideband management bus.

10. The system of claim 9, wherein the service processor limits access to the generated passcode to authenticated administrators with access to the remote access controller.

11. The system of claim 8, wherein the passcode is generated by hashing a serial number of the FPGA card with a service tag of the IHS (Information Handling System) in which the FPGA card is installed.

12. The system of claim 8, wherein the passcode is generated based on inputs provided via a user interface of the remote access controller.

13. The system of claim 8, wherein, upon enabling of the debug port, the debug port is disabled upon detecting de-coupling of a device from the debug port.

15. A remote access controller configured for securing access to an FPGA (Field Programmable Gate Array) card debug port, the remote access controller configured to:

determine a status of the FPGA card debug port via a query to a management controller of the FPGA card;

generate a passcode for the debug port;

disable the debug port via a message to the management controller;

detect a request for access to the debug port by a requestor, wherein the request includes a requestor password;

provide the requestor access to the debug port if the requestor password matches the generated passcode; and

disable the debug port upon the next power cycle of the FPGA card.

16. The remote access controller of claim 15, wherein the management controller communicates with a service processor of the remote access controller via a sideband management bus.

17. The remote access controller of claim 16, wherein the service processor limits access to the generated passcode to authenticated administrators with access to the remote access controller.

18. The remote access controller of claim 15, wherein the passcode is generated by hashing a serial number of the FPGA card with a service tag of the IHS (Information Handling System) in which the FPGA card is installed.

19. The remote access controller of claim 15, wherein the passcode is generated based on inputs provided via a user interface of the remote access controller.

20. The remote access controller of claim 15, wherein, upon enabling of the debug port, the debug port is disabled upon detecting de-coupling of a device from the debug port.