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TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION

  • US 20200132763A1
  • Filed: 12/05/2019
  • Published: 04/30/2020
  • Est. Priority Date: 01/24/2014
  • Status: Active Grant
First Claim
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1. A method for testing an application specific integrated circuit (ASIC), comprising:

  • identifying an ASIC sub-chip in the ASIC based on power dissipation and IR sensitivity by performing a functional mode analysis;

    performing test mode power analysis by;

    creating a set of representations that overlays power density information and clock gate physical locations of a set of clock gates in the ASIC sub-chip;

    grouping the set of representations in the sub-chip into multiple groups based on overlapping the set of representations;

    performing a test mode IR drop by;

    performing a static IR drop analysis to identify a set of hot spot regions in the ASIC sub-chip having a maximum average power hotspot, thenperforming a dynamic IR drop analysis to identify hot spot regions that have instantaneously high IR drop; and

    generating a set of test control signals to the set of clock gates during an at-speed test mode of operation such that each clock gate with overlapping representations has test control signals that are not activated simultaneously thereby avoiding simultaneous switching of the clock gates and resulting IR drop hotspots.

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