TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION

• US 20200132763A1
• Filed: 12/05/2019
• Published: 04/30/2020
• Est. Priority Date: 01/24/2014
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Agarwal, Khushboo, Hulical Vijayaraghavachar, Sanjay Krishna, Shaikh, Raashid Moin, Ravi, Srivaths, Pradeep, Wilson, Tiwari, Rajesh Kumar
• Granted Patent: US 11,333,707 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922

Abstract

Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

Claims

1. A method for testing an application specific integrated circuit (ASIC), comprising:

identifying an ASIC sub-chip in the ASIC based on power dissipation and IR sensitivity by performing a functional mode analysis;

performing test mode power analysis by;

creating a set of representations that overlays power density information and clock gate physical locations of a set of clock gates in the ASIC sub-chip;

grouping the set of representations in the sub-chip into multiple groups based on overlapping the set of representations;

performing a test mode IR drop by;

performing a static IR drop analysis to identify a set of hot spot regions in the ASIC sub-chip having a maximum average power hotspot, then

performing a dynamic IR drop analysis to identify hot spot regions that have instantaneously high IR drop; and

generating a set of test control signals to the set of clock gates during an at-speed test mode of operation such that each clock gate with overlapping representations has test control signals that are not activated simultaneously thereby avoiding simultaneous switching of the clock gates and resulting IR drop hotspots.

2. The method of claim 1, wherein creating a set of representations corresponding to each clock gate comprises:

identifying eligible clock gates of the set of clock gates;

extracting location and load information for each eligible clock gate of the set of clock gates; and

computing the representation for each eligible clock gate.

3. The method of claim 1, wherein grouping the set of representations in each sub-chip into various groups based on overlapping of representations comprises:

extracting a set of overlap graphs from the representations of the eligible clock gates; and

running a coloring scheme on each of the overlap graphs to determine a mapping of a preliminary test control signal of the set of test control signals to the set of clock gates.

4. The method of claim 3, wherein running a coloring scheme on each of the overlap graphs comprises:

creating a clock gate connectivity matrix; and

reassigning the color scheme incrementally across the set of overlap graphs.

5. The method of claim 1 further comprising:

generating patterns using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

6. The method of claim 5, wherein generating patterns comprises:

receiving a set of values of the set of test control signals;

checking for a contention corresponding to the set of values where more than one of the set of values is a logic 1; and

removing a pattern associated with contention dynamically during pattern generation.