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BUILT-IN SELF TEST CIRCUIT FOR MEASURING PHASE NOISE OF A PHASE LOCKED LOOP

  • US 20200132764A1
  • Filed: 09/18/2019
  • Published: 04/30/2020
  • Est. Priority Date: 10/31/2018
  • Status: Active Grant
First Claim
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1. An apparatus for measuring phase noise of a device under test (DUT), the apparatus comprising:

  • a first phase detector configured to receive a first signal from the DUT and first clock signal from a timing generator, wherein the first phase detector is further configured to measure a phase error between the first signal and the first clock signal and output a first phase error signal;

    a first charge pump configured to receive the first phase error signal and generate a first current;

    a first capacitor configured to receive the first current and provide a first voltage;

    a first voltage controlled delay line (VCDL) configured to receive a second clock signal and the first voltage, and output a first delay signal indicative of a delay proportional to the first voltage; and

    a first 1-bit time-to-digital converter (TDC) configured to receive a third clock signal and the first delay signal and output a first logical value if the first delay signal leads the third clock signal and output a second logical value if the first delay signal lags the third clock signal.

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