BUILT-IN SELF TEST CIRCUIT FOR MEASURING PHASE NOISE OF A PHASE LOCKED LOOP

• US 20200132764A1
• Filed: 09/18/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chou, Mao-Hsuan, Chang, Ya-Tin, Sheen, Ruey-Bin, Chang, Chih-Hsien
• Granted Patent: US 10,928,447 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).

Claims

1. An apparatus for measuring phase noise of a device under test (DUT), the apparatus comprising:

a first phase detector configured to receive a first signal from the DUT and first clock signal from a timing generator, wherein the first phase detector is further configured to measure a phase error between the first signal and the first clock signal and output a first phase error signal;

a first charge pump configured to receive the first phase error signal and generate a first current;

a first capacitor configured to receive the first current and provide a first voltage;

a first voltage controlled delay line (VCDL) configured to receive a second clock signal and the first voltage, and output a first delay signal indicative of a delay proportional to the first voltage; and

a first 1-bit time-to-digital converter (TDC) configured to receive a third clock signal and the first delay signal and output a first logical value if the first delay signal leads the third clock signal and output a second logical value if the first delay signal lags the third clock signal.

2. The apparatus of claim 1 further comprising:

a second phase detector configured to receive the first delay signal from the first VCDL and the first clock signal from the timing generator, wherein the second phase detector is further configured to measure a second phase error between the first delay signal and the first clock signal and output a second phase error signal;

a second charge pump configured to receive the second phase error signal and generate a second current;

a second capacitor configured to receive the second current and provide a second voltage;

a second VCDL configured to receive the second clock signal and the second voltage, and output a second delay signal indicative of a second delay proportional to the second voltage; and

a second 1-bit TDC configured to receive the third clock signal and the second delay signal and output the first logical value if the second delay signal leads the third clock signal and output the second logical value if the second delay signal lags the third clock signal.

3. The apparatus of claim 2 further comprising:

a third phase detector configured to receive the second delay signal from the second VCDL and the first clock signal from the timing generator, wherein the third phase detector is further configured to measure a third phase error between the second delay signal and the first clock signal and output a third phase error signal;

a third charge pump configured to receive the third phase error signal and generate a third current;

a third capacitor configured to receive the third current and provide a third voltage;

a third VCDL configured to receive the second clock signal and the third voltage, and output a third delay signal indicative of a third delay proportional to the third voltage; and

a third 1-bit TDC configured to receive the third clock signal and the third delay signal and output the first logical value if the third delay signal leads the third clock signal and output the second logical value if the third delay signal lags the third clock signal.

4. The apparatus of claim 3 wherein:

the third clock signal comprises a reference clock signal (Fref);

the second clock signal comprises Fref−

(K×

Δ

θ

), where K is a predetermined integer greater than one and Δ

θ

is predetermined phase skew; and

the first clock signal comprises one of Fref+Δ

θ

or Fref−

Δ

θ

.

5. The apparatus of claim 4 further comprising:

a first multiplexer having a first input configured to receive Fref+Δ

θ

, a second input configured to receive Fref−

Δ

θ

, and a first control input configured to receive a first digital output of the first 1-bit TDC at a control input, wherein a value of the first digital output selects either Fref+Δ

θ

or Fref−

Δ

θ

to be output by the first multiplexer and provided to the first phase detector;

a second multiplexer having a third input configured to receive Fref+Δ

θ

, a fourth input configured to receive Fref−

Δ

θ

, and a second control input configured to receive a second digital output of the second 1-bit TDC, wherein a value of the second digital output selects either Fref+Δ

θ

or Fref−

Δ

θ

to be output by the second multiplexer and provided to the second phase detector; and

a third multiplexer having a fifth input configured to receive Fref+Δ

θ

, a sixth input configured to receive Fref−

Δ

θ

, and a third control input configured to receive a third digital output of the third 1-bit TDC, wherein a value of the third digital output selects either Fref+Δ

θ

or Fref−

Δ

θ

to be output by the third multiplexer and provided to the third phase detector.

6. The apparatus of claim 4 further comprising a timing generator configured to generate the first, second and third clock signals.

7. The apparatus of claim 3 wherein the DUT comprises a phase locked loop (PLL) and the first signal comprises a feedback signal of the PLL having a frequency equal to an output frequency of the PLL divided by N, where N is a predetermined integer greater than 1.

8. The apparatus of claim 1 wherein:

the third clock signal comprises a reference clock signal (Fref);

the second clock signal comprises Fref−

(K×

Δ

θ

), where K is a predetermined integer greater than one and Δ

θ

is predetermined phase skew; and

the first clock signal comprises one of Fref+Δ

θ

or Fref−

Δ

θ

.

9. The apparatus of claim 8 further comprising:

a first multiplexer having a first input configured to receive Fref+Δ

θ

, a second input configured to receive Fref−

Δ

θ

, and a first control input configured to receive a first digital output of the first 1-bit TDC at a control input, wherein a value of the first digital output selects either Fref+Δ

θ

or Fref−

Δ

θ

to be output by the first multiplexer and provided to the first phase detector.

10. The apparatus of claim 8 further comprising a timing generator configured to generate the first, second and third clock signals.

11. A multi-stage noise shaping (MASH) type high-order delta sigma (Δ

Σ

) time-to-digital converter (TDC), comprising;

a first first-order Δ

Σ

TDC configured to receive a first signal from a device under test (DUT) and a first clock signal, wherein the first first-order Δ

Σ

TDC is configured to measure a phase difference between the first signal and the first clock signal and convert the phase difference to a first digital value; and

a second first-order Δ

Σ

TDC configured to receive a first residue signal from the first first-order Δ

Σ

TDC and the first clock signal, wherein the second first-order Δ

Σ

TDC is configured to measure a phase difference between the first residue signal and the first clock signal and convert the phase difference to a second digital value.

12. The MASH type high-order Δ

Σ

TDC of claim 11, wherein the first first-order Δ

Σ

TDC comprises;

a first phase detector configured to receive a first signal from the DUT and first clock signal from a timing generator, wherein the first phase detector is further configured to measure a phase error between the first signal and the first clock signal and output a first phase error signal;

a first charge pump configured to receive the first phase error signal and generate a first current;

a first capacitor configured to receive the first current and provide a first voltage;

a first voltage controlled delay line (VCDL) configured to receive a second clock signal and the first voltage, and output a first delay signal indicative of a delay proportional to the first voltage; and

a first 1-bit time-to-digital converter (TDC) configured to receive a third clock signal and the first delay signal and output a first logical value if the first delay signal leads the third clock signal and output a second logical value if the first delay signal lags the third clock signal.

13. The MASH type high-order Δ

Σ

TDC of claim 12, wherein the second first-order Δ

Σ

TDC comprises;

a second phase detector configured to receive the first delay signal from the first VCDL and the first clock signal from the timing generator, wherein the second phase detector is further configured to measure a second phase error between the first delay signal and the first clock signal and output a second phase error signal;

a second charge pump configured to receive the second phase error signal and generate a second current;

a second capacitor configured to receive the second current and provide a second voltage;

a second VCDL configured to receive the second clock signal and the second voltage, and output a second delay signal indicative of a second delay proportional to the second voltage; and

a second 1-bit TDC configured to receive the third clock signal and the second delay signal and output the first logical value if the second delay signal leads the third clock signal and output the second logical value if the second delay signal lags the third clock signal.

14. The MASH type high-order Δ

Σ

TDC of claim 13, wherein;

the third clock signal comprises a reference clock signal (Fref);

the second clock signal comprises Fref−

(K×

Δ

θ

), where K is a predetermined integer greater than one and Δ

θ

is predetermined phase skew; and

the first clock signal comprises one of Fref+Δ

θ

or Fref−

Δ

θ

.

15. The MASH type high-order Δ

Σ

TDC of claim 14, further comprising;

a first multiplexer having a first input configured to receive Fref+Δ

θ

, a second input configured to receive Fref−

Δ

θ

, and a first control input configured to receive a first digital output of the first 1-bit TDC at a control input, wherein a value of the first digital output selects either Fref+Δ

θ

or Fref−

Δ

θ

to be output by the first multiplexer and provided to the first phase detector; and

a second multiplexer having a third input configured to receive Fref+Δ

θ

, a fourth input configured to receive Fref−

Δ

θ

, and a second control input configured to receive a second digital output of the second 1-bit TDC, wherein a value of the second digital output selects either Fref+Δ

θ

or Fref−

Δ

θ

to be output by the second multiplexer and provided to the second phase detector.

16. The MASH type high-order Δ

Σ

TDC of claim 14, further comprising a timing generator configured to generate the first, second and third clock signals.

17. The MASH type high-order Δ

Σ

TDC of claim 13, wherein the DUT comprises a phase locked loop (PLL) and the first signal comprises a feedback signal of the PLL having a frequency equal to an output frequency of the PLL divided by N, where N is a predetermined integer greater than 1.

18. A method of converting noise into a digital signal, the method comprising:

providing a first reference signal to a device under test (DUT) and a first node of a first delta sigma (Δ

Σ

) time-to-digital converter (TDC);

providing a first feedback signal from the DUT to a second node of the first Δ

Σ

TDC;

providing a second reference signal to a third node of the first Δ

Σ

TDC;

providing a third and a fourth reference signal to a fourth and a fifth node, respectively, of the first Δ

Σ

TDC;

providing a first output of the first Δ

Σ

TDC as a second feedback signal to a sixth node of the first Δ

Σ

TDC, wherein the second feedback signal selects either the third or fourth reference signal to provide to a seventh node of the first Δ

Σ

TDC; and

saving a digital output of the first Δ

Σ

TDC in a memory.

19. The method of claim 18 further comprising:

providing the first reference signal to a first node of a second Δ

Σ

TDC;

providing the second reference to a second node of the second Δ

Σ

TDC;

providing the third and fourth reference signals to a third node and a fourth node, respectively, of the second Δ

Σ

TDC;

providing a second output of the first Δ

Σ

TDC to a fifth node of a second Δ

Σ

TDC;

providing a first output of the second Δ

Σ

TDC as a third feedback signal to a sixth node of the second Δ

Σ

TDC, wherein the third feedback signal selects either the third or fourth reference signal to provide to a seventh node of the second Δ

Σ

TDC; and

saving a digital output of the second Δ

Σ

TDC in a memory.

20. The method of claim 19 wherein each of the first and second Δ

Σ

TDCs is configured to provide a digital output signal to a controller for processing, wherein the digital output signal is representative of a phase noise of the DUT.