TEST APPARATUS

• US 20200132765A1
• Filed: 01/02/2020
• Published: 04/30/2020
• Est. Priority Date: 12/07/2016
• Status: Active Grant

• Current Assignee: Korea University Research and Business Foundation (Korea University), SK Hynix Inc.
• Original Assignee: Korea University Research and Business Foundation (Korea University), SK Hynix Inc.
• Inventors: KIM, Chul Woo, KIM, Dong Yoon, JUNG, In Hwa, KIM, Yong Ju
• Granted Patent: US 10,983,164 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/286 External aspects, e.g. related to chambers, contacting devices or handlers
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers , and provides the second timing information corresponding to the timing differences to the transceivers.

Claims

1. A method of testing a plurality of devices under test (DUTs), the method comprising:

determining, by a test apparatus in a training mode, a first delay of up to a unit interval;

determining, by the test apparatus in the training mode, a second delay corresponding to an integer multiple of the predetermined unit interval;

delaying, by the test apparatus in an operation mode, a data signal by the second delay to produce a delayed data signal; and

delaying, by the test apparatus in the operation mode, the delayed data signal by the first delay to produce a compensated data signal.

2. The method of claim 1, wherein the second delay corresponds to a difference between a delay of a first transducer of a plurality of transducers and a delay of a second transducer of the plurality of transducers, the second transducer being a lowest transducer of the plurality of transducers.

3. The method of claim 1, wherein the first delay corresponds to a delay between a transition of a test data signal and a transition of a clock signal.

4. The method of claim 1, wherein the first delay is determined in the training mode by a Delay Locked Loop (DLL).

5. The method of claim 1, wherein delaying, by the test apparatus in the operation mode, the delayed data signal by the first delay to produce a compensated data signal comprises:

delaying a clock signal by the first delay to produce a delayed clock signal; and

latching the delayed data signal using the delayed clock signal.