PROCEDURE FOR REVIEWING AN FPGA-PROGRAM

• US 20200132766A1
• Filed: 10/28/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Dspace GmbH
• Original Assignee: Dspace Digital Signal Processing And Control Engineering Gmbh
• Inventors: Kalte, Heiko, Lubeley, Dominik
• Granted Patent: US 11,187,748 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory

Abstract

A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

Claims

1. A method for detecting errors of a first field-programmable gate array (FPGA) program, comprising:

receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and

comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

2. The method as recited in claim 1, wherein a plurality of comparisons between signal values and reference values are performed and combined.

3. The method as recited in claim 2, wherein respective signal values are compared to reference values more frequently based on memory locations and/or logic elements corresponding to the respective signal values being exposed to a higher thermal load relative to other signal values corresponding to memory locations and/or logic elements exposed to a lower thermal load.

4. The method as recited in claim 3, wherein thermal load on memory locations is estimated via simulation.

5. The method as recited in claim 1, wherein the reference value is a predefined value.

6. The method as recited in claim 1, wherein the signal value and the reference value each specify a memory address in the BlockRAM of the FPGA.

7. The method as recited in claim 1, wherein an error of the first FPGA program is detected based on the signal value being greater than a first reference value and/or less than a second reference value.

8. The method as recited in claim 1, wherein the reference value is set after a write access to the BlockRAM of the FPGA.

9. The method as recited in claim 6, wherein the BlockRAM is divided into a plurality of partitions, and at least one reference value is used for each partition.

10. The method as recited in claim 1, wherein the processor is connected to a further FPGA, and the reference value is read out from the further FPGA.

11. The method as recited in claim 1, wherein the reference value is dynamically generated in the processor.

12. The method as recited in claim 1, wherein the monitoring program sends a stimulation value to the FPGA.

13. The method as recited in claim 12, wherein the stimulation value overwrites a constant in the first FPGA program.

14. The method as recited in claim 1, wherein the signal value is read out from the FPGA via readback.

15. A system, comprising:

a processor configured to execute a monitoring program; and

a field-programmable gate array (FPGA) configured to execute a first FPGA program;

wherein the first FPGA program is configured to read out a signal value and supply the signal value to the monitoring program; and

wherein the monitoring program is configured to compare the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.

16. A non-transitory computer-readable medium having processor-executable instructions stored thereon for detecting errors of a first field-programmable gate array (FPGA) program executed on an FPGA, the processor-executable instructions, when executed by a processor, facilitating:

receiving a signal value read out from the first FPGA program; and

comparing the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.