PROCEDURE FOR REVIEWING AN FPGA-PROGRAM
First Claim
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1. A method for detecting errors of a first field-programmable gate array (FPGA) program, comprising:
- receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and
comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.
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Abstract
A method for detecting errors of a first field-programmable gate array (FPGA) program includes: receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.
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Citations
16 Claims
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1. A method for detecting errors of a first field-programmable gate array (FPGA) program, comprising:
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receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A system, comprising:
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a processor configured to execute a monitoring program; and a field-programmable gate array (FPGA) configured to execute a first FPGA program; wherein the first FPGA program is configured to read out a signal value and supply the signal value to the monitoring program; and wherein the monitoring program is configured to compare the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.
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16. A non-transitory computer-readable medium having processor-executable instructions stored thereon for detecting errors of a first field-programmable gate array (FPGA) program executed on an FPGA, the processor-executable instructions, when executed by a processor, facilitating:
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receiving a signal value read out from the first FPGA program; and comparing the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program.
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Specification