SCAN CHAIN TECHNIQUES AND METHOD OF USING SCAN CHAIN STRUCTURE

• US 20200132767A1
• Filed: 10/18/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: HAI, Yisu, SONG, Jonguk
• Granted Patent: US 11,156,664 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/31853 Test of registers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318597 JTAG or boundary scan test of memory devices other scan testing of memories G11C29/32
• CPC Class Codes: G11C 2029/1806 Address conversion or mapping, i.e. logical to physical address
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

Testing systems and method of testing an integrated circuit are provided. A testing system comprises an input terminal, multiple circuit elements, each having a register, and an output terminal forming a scan chain through which an input signal is propagated. The testing system further comprises a debugger that includes a mapping module that stores information mapping register values to their respective functional meanings. The input signal is applied to extract all values of all of the registers whether or not accessible by a processor.

Claims

1. A testing system comprising:

an input terminal, a plurality of circuit elements, each having a register, and an output terminal forming a scan chain through which an input signal is propagated; and

a debugger that includes a mapping module that stores information mapping register values to their respective functional meanings,

wherein the input signal is applied to extract all values of all of the registers whether or not accessible by a processor.

2. The testing system of claim 1, wherein the plurality of circuit elements include a plurality of flip-flops.

3. The testing system of claim 2, further comprising an integrated circuit that includes the plurality of flip-flops.

4. The testing system of claim 1, wherein the mapping module includes a mapping table with an index for position of the values as extracted and an index for functional meaning.

5. The testing system of claim 4, wherein the functional meaning index includes, for each value in the position index, information identifying a block and the circuit element in which the register associated with that value is embodied.

6. The testing system of claim 1, wherein respective subsets of the plurality of circuit elements are embodied in respective blocks, and the mapping module includes multiple mapping tables, one for each of the blocks.

7. A system comprising:

a computer, including a mapping module, configured to apply an input signal to a scan chain and to receive an output of the scan chain; and

an integrated circuit including a plurality of combinatorial logic elements of the scan chain;

wherein the mapping module is configured to capture at least one value of each of the plurality of combinatorial logic elements whether or not accessible by a processor.

8. The system of claim 7, wherein the plurality of combinatorial logic elements includes a plurality of flip-flops.

9. The system of claim 7, wherein the mapping module includes a mapping table with an index for bit position and an index for the functional meaning.

10. A method of testing an integrated circuit including a plurality of circuit elements, each having a register storing a value, the method comprising:

generating mapping information identifying each of the plurality of circuit elements in terms of a hierarchical position within the integrated circuit;

propagating an input signal through the plurality of circuit elements to form a scan chain;

receiving an output signal containing the values of the plurality of registers of the scan chain; and

correlating a position of each of the values in the output signal to its functional meaning using the mapping information;

wherein all of the values of all of the registers are obtained whether or not accessible by a processor.

11. The method of claim 10, wherein the mapping information is maintained in a mapping table.

12. The method of claim 11, wherein the mapping table has an index for position of the values as extracted and an index for functional meaning.

13. The method of claim 12, wherein the functional meaning index includes, for each value in the position index, information identifying a block and the circuit element in which the register associated with that value is embodied.