DISPLAY PANEL, METHOD FOR MAKING THE SAME AND METHOD FOR CONTROLLING THE SAME

• US 20200133084A1
• Filed: 01/02/2018
• Published: 04/30/2020
• Est. Priority Date: 11/29/2017
• Status: Active Grant

• Current Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: HONG, Guanghui, GONG, Qiang
• Granted Patent: US 10,747,076 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2001/1678 characterised by the composition or particle type
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2310/0245 Clearing or presetting the whole screen independently of waveforms, e.g. on power-on G09G2310/063 takes precedence
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

The disclosure provides a display panel, a method for making the display panel, and a method for controlling the display panel. The display panel comprises: multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions; multiple pixel electrodes in the multiple pixel regions; multiple first thin film transistors in the multiple pixel regions, the gates of the multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; and a second thin film transistor between and connecting two adjacent pixel electrodes, wherein the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state when the display panel is under a power failure condition.

Claims

1. A display panel, comprising

multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions;

multiple pixel electrodes in the multiple pixel regions;

multiple first thin film transistors in the multiple pixel regions, wherein each of the multiple first thin film transistors comprises a gate, source and a drain, the gates of the multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; and

a second thin film transistor between and connecting two adjacent pixel electrodes, wherein the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state when the display panel is under a power failure condition.

2. The display panel according to claim 1, further comprising a global signal line between two adjacent gate lines, wherein the second thin film transistor comprises a gate connected to the global signal line, and the second thin film transistor further comprises a source and a drain connected to the two pixel electrodes adjacent to the second thin film transistor respectively.

3. The display panel according to claim 2, when the display panel is under normal operation, a voltage that the global signal line applied to the gate of the second thin film transistor is VGL (voltage gate low), and when the display panel is under a power failure condition, the voltage that the global signal line applied to the gate of the second thin film transistor is VGH (voltage gate high) and maintains for a period of time.

4. The display panel according to claim 3, after the voltage that the global signal line applied to the gate of the second thin film transistor is voltage gate high and maintains for a period of time, wherein the pixel regions in the display panel are at the lower positive potential with the same charge amount, at the lower negative potential with the same charge amount or at the same ground potential (GND).

5. The display panel according to claim 1, wherein the second thin film transistor is an n-type thin film transistor.

6. A method for making a display panel, comprising:

disposing multiple gate lines and multiple data line on a substrate, wherein the multiple data line cross the multiple gate lines to form multiple pixel regions;

disposing multiple first thin film transistors and multiple pixel electrodes in the multiple pixel regions, wherein each of the multiple first thin film transistors comprises a gate, source and a drain, connecting the gates of multiple first thin film transistors to the gate lines, and connecting the sources and the drains of the multiple first thin film transistor to the gate lines and the data lines respectively;

disposing a second thin film transistor between two adjacent pixel electrodes, wherein the second thin film transistor is in a non-conducting state when the display panel is under normal operation, and the second thin film transistor is in a conducting state when the display panel is under a power failure condition.

7. The method according to claim 6, further comprising:

disposing a global signal line between two adjacent gate lines, connecting the gate of the second thin film transistor to the global signal line, connecting the source and the drain of the second thin film transistor the two pixel electrodes adjacent to the second thin film transistor respectively.

8. A method for controlling the display panel, wherein the display panel comprises multiple gate lines and multiple data line crossing the multiple gate lines to form multiple pixel regions;

multiple pixel electrodes in the multiple pixel regions;

multiple first thin film transistors in the multiple pixel regions, wherein each of the multiple first thin film transistors comprises a gate, source and a drain, the gates of multiple first thin film transistors are connected to the gate lines, and the sources and the drains are connected to the data lines and the pixel electrodes respectively; and

a second thin film transistor between and connecting two adjacent pixel electrodes, wherein the method comprises;

when the display panel is under normal operation, the second thin film transistor is in a non-conducting state, and when the display panel is under a power failure condition, the second thin film transistor is in a conducting state.

9. The method according to claim 8, wherein the display panel further comprises a global signal line between two adjacent gate lines, wherein the second thin film transistor comprises a gate connected to the global signal line, and the second thin film transistor further comprises a source and a drain connected to the two pixel electrodes adjacent to the second thin film transistor respectively, wherein the method further comprises:

when the display panel is under normal operation, the global signal line applies a voltage gate low (VGL) to the gate of the second thin film transistor, and when the display panel is under a power failure condition, the global signal line applies a voltage gate high to the gate of the second thin film transistor for a period of time.

10. The method according to claim 9, after the voltage that the global signal line applied to the gate of the second thin film transistor is voltage gate high and maintains for a period of time, the pixel regions in the display panel are at the lower positive potential with the same charge amount, at the lower negative potential with the same charge amount or at the same ground potential (GND).