DEVICE AND METHOD FOR CALIBRATING A VOLTAGE REGULATOR

• US 20200133321A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Jeong, Jae Woong, Winemberg, LeRoy
• Granted Patent: US 10,613,561 B1
• Time in Patent Office: Days
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

An integrated circuit includes a voltage monitor circuit having a first input coupled to a reference voltage and a second input, a successive approximation register (SAR) circuit having an input coupled to an output of the voltage monitor circuit, a low drop out (LDO) regulator having an input coupled to an output of the SAR circuit and an output coupled to the second input, a discharge circuit coupled to the LDO output, voltage sensing circuit having a first input coupled to the reference voltage during a trim mode and coupled to the LDO output during a monitor mode, having a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the first input goes higher or lower than the reference voltage by a predetermined amount. Control circuitry is configured to, during trim mode, periodically discharge the LDO output voltage.

Claims

1. An integrated circuit comprising:

a voltage monitor circuit having a first input coupled to a reference voltage and a second input;

a successive approximation register (SAR) circuit having an input coupled to an output of the voltage monitor circuit;

a low drop out (LDO) regulator having an input coupled to an output of the SAR circuit and an output coupled to the second input and which provides an LDO output;

a discharge circuit coupled to the LDO output;

voltage sensing circuit having a first input coupled to the reference voltage during a trim mode and coupled to the LDO output during a monitor mode, having a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the first input goes higher or lower than the reference voltage by a predetermined amount; and

control circuitry configured to;

control transition from the monitor mode to the trim mode in response to assertion of the sense indicator; and

during trim mode, control the discharge circuit to periodically discharge the LDO output voltage.

2. The integrated circuit of claim 1, wherein the SAR circuit comprises:

SAR control circuitry which is configured to be reset in response to assertion of the sense indicator and has an input coupled to the output of the voltage monitor circuit; and

a variable resistance circuit coupled between outputs of the SAR control circuitry and the input of the LDO regulator circuit.

3. The integrated circuit of claim 2, wherein the SAR control circuitry is configured to, during trim mode, sequentially set the outputs of the SAR control circuitry based on comparisons between the reference voltage and the LDO output voltage.

4. The integrated circuit of claim 3, wherein a resistance value of the variable resistance circuit at the first input of the LDO regulator circuit is determined by the outputs of the SAR control circuitry.

5. The integrated circuit of claim 3, wherein the control circuitry is configured to, during trim mode, enable the discharge circuit to discharge the LDO output prior to setting each output of the SAR control circuitry based on the comparison between the reference voltage and the LDO output voltage.

6. The integrated circuit of claim 5, wherein the trim mode ends after sequentially setting all the outputs of the SAR control circuitry.

7. The integrated circuit of claim 6, wherein the monitor mode follows the trim mode in which the first input of the voltage sensing circuit is coupled to the LDO output and not the reference voltage.

8. The integrated circuit of claim 1, wherein asserting the sense indicator comprises providing a pulse to the SAR circuit to reset the SAR circuitry and to the control circuitry to initiate a trim mode.

9. The integrated circuit of claim 8, wherein the control circuitry is configured to control the duration of the trim mode.

10. The integrated circuit of claim 1, wherein the voltage sensing circuit comprises:

a first comparator having an inverting input coupled to the first input of the voltage sensing circuit and a non-inverting input coupled to the reference voltage; and

a second comparator having an inverting input coupled to the reference voltage and a non-inverting input coupled to the second input of the voltage sensing circuit.

11. The integrated circuit of claim 10, wherein the voltage sensing circuit further comprises:

first pulse generating circuitry coupled to an output of the first comparator; and

second pulse generating circuitry coupled to an output of the second comparator, wherein;

the first pulse generating circuitry is configured to provide the asserted sense indicator when the voltage at the first input of the voltage sensing circuit goes lower than the reference voltage, and

the second pulse generating circuitry is configured to provide the asserted sense indicator when the voltage at the first input of the voltage sensing circuit goes higher than the reference voltage.

12. The integrated circuit of claim 11, further comprising:

a switch having a first input coupled to the reference voltage, a second input coupled to the receive the LDO output, an output coupled to the first input of the voltage sensing circuit, and a control input coupled to the control circuitry, wherein the switch is configured to couple the first input of the switch to the output of the switch during the trim mode and to couple the second input of the switch to the output of the switch during the monitor mode.

13. An integrated circuit comprising:

a low drop out (LDO) regulator having an output which provides an LDO output; and

voltage sensing circuit having a first input coupled to a reference voltage during a trim mode and coupled to the LDO output during a monitor mode, a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the second input goes higher than the reference voltage by a first predetermined amount and alternatively when the voltage at the second input goes lower than the reference voltage by a second predetermined amount.

14. The integrated circuit of claim 13, wherein the voltage sensing circuit comprises:

a first comparator having an inverting input coupled to the first input of the voltage sensing circuit and a non-inverting input coupled to the second input of the voltage sensing circuit; and

a second comparator having an inverting input coupled to the reference voltage and a non-inverting input coupled to the second input of the voltage sensing circuit.

15. The integrated circuit of claim 14, wherein the voltage sensing circuit further comprises:

first pulse generating circuitry coupled to an output of the first comparator;

second pulse generating circuitry coupled to an output of the second comparator, wherein;

the first pulse generating circuitry has an output and is configured to provide the asserted sense indicator when the voltage at the first input of the voltage sensing circuit goes lower than the reference voltage by the second predetermined amount, and

the second pulse generating circuitry has an output and is configured to provide the asserted sense indicator when the voltage at the first input of the voltage sensing circuit goes higher than the reference voltage by the first predetermined amount.

16. The integrated circuit of claim 15, further comprising:

an OR gate having a first input coupled to the output of the first pulse generating circuitry, a second input coupled to the output of the second pulse generating circuitry, and an output coupled to the output of the voltage sensing circuitry.

17. The integrated circuit of claim 15, wherein the first pulse generating circuitry comprises first wave shaping circuitry configured to shape the output of the first comparator and the second pulse generating circuitry comprises second wave shaping circuitry configured to shape the output of the second comparator.

18. In an integrated circuit configured to operate in a monitor mode and in a trim mode and having a low drop out (LDO) regulator and a successive approximation register (SAR) circuit having a variable resistance coupled to an input of the LDO regulator circuit, a method comprising:

during the monitor mode;

comparing an output of the LDO regulator circuit with a reference voltage;

asserting a sense indicator when a voltage at the output of the LDO regulator circuit goes higher or lower than the reference voltage by a predetermined amount;

in response to asserting the sense indicator, entering a trim mode and resetting the SAR circuit;

during the trim mode;

after the resetting the SAR circuit, sequentially varying a resistance of the SAR circuit coupled to the input of the LDO regulator circuit based on a difference between a voltage at the output of the LDO and the reference voltage, wherein the method further includes, prior to each varying of the resistance of the SAR circuit, discharging the LDO output voltage.

19. The method of claim 18, further comprising:

after varying the resistance of the SAR circuit a predetermined number of times, exiting the trim mode and entering the monitor mode.

20. The method of claim 18, wherein asserting the sense indicator comprises providing a pulse to reset the SAR circuit and initiate the trim mode.