DEVICE AND METHOD FOR CALIBRATING A VOLTAGE REGULATOR
First Claim
1. An integrated circuit comprising:
- a voltage monitor circuit having a first input coupled to a reference voltage and a second input;
a successive approximation register (SAR) circuit having an input coupled to an output of the voltage monitor circuit;
a low drop out (LDO) regulator having an input coupled to an output of the SAR circuit and an output coupled to the second input and which provides an LDO output;
a discharge circuit coupled to the LDO output;
voltage sensing circuit having a first input coupled to the reference voltage during a trim mode and coupled to the LDO output during a monitor mode, having a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the first input goes higher or lower than the reference voltage by a predetermined amount; and
control circuitry configured to;
control transition from the monitor mode to the trim mode in response to assertion of the sense indicator; and
during trim mode, control the discharge circuit to periodically discharge the LDO output voltage.
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Accused Products
Abstract
An integrated circuit includes a voltage monitor circuit having a first input coupled to a reference voltage and a second input, a successive approximation register (SAR) circuit having an input coupled to an output of the voltage monitor circuit, a low drop out (LDO) regulator having an input coupled to an output of the SAR circuit and an output coupled to the second input, a discharge circuit coupled to the LDO output, voltage sensing circuit having a first input coupled to the reference voltage during a trim mode and coupled to the LDO output during a monitor mode, having a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the first input goes higher or lower than the reference voltage by a predetermined amount. Control circuitry is configured to, during trim mode, periodically discharge the LDO output voltage.
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Citations
20 Claims
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1. An integrated circuit comprising:
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a voltage monitor circuit having a first input coupled to a reference voltage and a second input; a successive approximation register (SAR) circuit having an input coupled to an output of the voltage monitor circuit; a low drop out (LDO) regulator having an input coupled to an output of the SAR circuit and an output coupled to the second input and which provides an LDO output; a discharge circuit coupled to the LDO output; voltage sensing circuit having a first input coupled to the reference voltage during a trim mode and coupled to the LDO output during a monitor mode, having a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the first input goes higher or lower than the reference voltage by a predetermined amount; and control circuitry configured to; control transition from the monitor mode to the trim mode in response to assertion of the sense indicator; and during trim mode, control the discharge circuit to periodically discharge the LDO output voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An integrated circuit comprising:
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a low drop out (LDO) regulator having an output which provides an LDO output; and voltage sensing circuit having a first input coupled to a reference voltage during a trim mode and coupled to the LDO output during a monitor mode, a second input coupled to the reference voltage, and an output which asserts a sense indicator that indicates when a voltage at the second input goes higher than the reference voltage by a first predetermined amount and alternatively when the voltage at the second input goes lower than the reference voltage by a second predetermined amount. - View Dependent Claims (14, 15, 16, 17)
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18. In an integrated circuit configured to operate in a monitor mode and in a trim mode and having a low drop out (LDO) regulator and a successive approximation register (SAR) circuit having a variable resistance coupled to an input of the LDO regulator circuit, a method comprising:
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during the monitor mode; comparing an output of the LDO regulator circuit with a reference voltage; asserting a sense indicator when a voltage at the output of the LDO regulator circuit goes higher or lower than the reference voltage by a predetermined amount; in response to asserting the sense indicator, entering a trim mode and resetting the SAR circuit; during the trim mode; after the resetting the SAR circuit, sequentially varying a resistance of the SAR circuit coupled to the input of the LDO regulator circuit based on a difference between a voltage at the output of the LDO and the reference voltage, wherein the method further includes, prior to each varying of the resistance of the SAR circuit, discharging the LDO output voltage. - View Dependent Claims (19, 20)
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Specification