RECEPTION DEVICE, OPERATING METHOD, AND TRANSMISSION SYSTEM WITH SWITCHING NOISE REDUCTION

• US 20200133329A1
• Filed: 09/30/2019
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: ROH, Gil Sung, KIM, Sang Kyung, HA, Ji Hoon
• Granted Patent: US 11,467,623 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal

Abstract

A reception device that communicates with a transmission device is provided. The reception device includes a reception circuit configured to receive a clock signal, a first data signal, and a second data signal from the transmission device, a signal synchronization circuit configured to adjust the phases of the first data signal and the second data signal, and generate a first synchronization data signal and a second synchronization data signal, a signal distribution circuit configured to adjust the phase of the clock signal and generate a first distributed clock signal and a second distributed clock signal, and adjust the phases of the first synchronization data signal and the second synchronization data signal and generate a first distributed data signal and a second distributed data signal, and an output circuit configured to process the first distributed data signal and the second distributed data signal.

Claims

1. A reception device that communicates with a transmission device, the reception device comprising:

a reception circuit configured to receive a clock signal, a first data signal, and a second data signal from the transmission device;

a signal synchronization circuit configured to adjust a phase of the first data signal and a phase of the second data signal, and generate a first synchronization data signal and a second synchronization data signal;

a signal distribution circuit configured to adjust a phase of the clock signal and generate a first distributed clock signal and a second distributed clock signal, and further configured to adjust a phase of the first synchronization data signal and a phase of the second synchronization data signal, and generate a first distributed data signal and a second distributed data signal; and

an output circuit configured to process the first distributed data signal and the second distributed data signal.

2. The device of claim 1, wherein the first synchronization data signal and the second synchronization data signal have a same phase.

3. The device of claim 1,

wherein a phase of the first distributed data signal and a phase of the second distributed data signal are different from each other, and

wherein a phase difference between the first distributed clock signal and the first distributed data signal is equal to a phase difference between the second distributed clock signal and the second distributed data signal.

4. The device of claim 3,

wherein the signal distribution circuit comprises:

a first delay circuit configured to adjust the phase of the clock signal and the phase of the first synchronization data signal by a first delay value and generate the first distributed clock signal and the first distributed data signal; and

a second delay circuit configured to adjust the phase of the clock signal and the phase of the second synchronization data signal by a second delay value different from the first delay value, and generate the second distributed clock signal and the second distributed data signal.

5. The device of claim 1,

wherein the output circuit is configured to process the first distributed data signal in response to the first distributed clock signal, and process the second distributed data signal in response to the second distributed clock signal.

6. The device of claim 5,

wherein a processing timing of the first distributed data signal and a processing timing of the second distributed data signal are different from each other.

7. The device of claim 1,

wherein a transmission line through which the clock signal is transmitted, a transmission line through which the first data signal is transmitted, and a transmission line through which the second data signal is transmitted are different from each other.

8. A method for operating a reception device that communicates with a transmission device and processes signals, the method comprising:

receiving a clock signal, a first data signal, and a second data signal from the transmission device;

adjusting a phase of the first data signal and a phase of the second data signal, and generating a first synchronization data signal and a second synchronization data signal;

adjusting a phase of the clock signal and generating a first distributed clock signal and a second distributed clock signal, and adjusting a phase of the first synchronization data signal and a phase of the second synchronization data signal, and generating a first distributed data signal and a second distributed data signal; and

processing the first distributed data signal and the second distributed data signal.

9. The method of claim 8,

wherein the phase of the first distributed data signal and the phase of the second distributed data signal are different from each other, and

wherein a phase difference between the first distributed clock signal and the first distributed data signal is equal to a phase difference between the second distributed clock signal and the second distributed data signal.

10. The method of claim 9, further comprising

adjusting the phase of the clock signal and the phase of the first synchronization data signal by a first delay value and generating the first distributed clock signal and the first distributed data signal;

and

adjusting the phase of the clock signal and the phase of the second synchronization data signal by a second delay value different from the first delay value and generating the second distributed clock signal and the second distributed data signal.

11. The method of claim 8,

wherein the processing of the first distributed data signal and the second distributed data signal comprises:

processing the first distributed data signal in response to the first distributed clock signal, and processing the second distributed data signal in response to the second distributed clock signal.

12. The method of claim 8,

wherein the clock signal is transmitted through a clock transmission line, and

wherein the first data signal and the second data signal are transmitted through at least one data transmission line.

13. The method of claim 8, wherein the transmission device and the reception device implement a mobile industry processor interface (MIPI).

14. A reception device that communicates with a transmission device, the reception device comprising:

a reception circuit configured to receive a clock signal, a first data signal, and a second data signal from the transmission device; and

a signal distribution circuit configured to generate a first distributed clock signal and a second distributed clock signal based on the clock signal, generate a first distributed data signal based on the first data signal, and generate a second distributed data signal based on the second data signal,

wherein a phase of the first distributed data signal and a phase of the second distributed data signal are different from each other, and

wherein a phase difference between the first distributed clock signal and the first distributed data signal is equal to a phase difference between the second distributed clock signal and the second distributed data signal.

15. The device of claim 14, further comprising

an output circuit configured to process the first distributed data signal in response to the first distributed clock signal, and process the second distributed data signal in response to the second distributed clock signal.

16. The device of claim 15, wherein a processing timing of the first distributed data signal and a processing timing of the second distributed data signal are different from each other.

17. A reception device comprising:

a reception circuit configured to receive a clock signal and a plurality of data signals; and

a signal distribution circuit configured to receive the clock signal and the plurality of data signals, adjust a phase of each of the plurality of data signals, and generate a plurality of distributed data signals based on the adjusted phases,

wherein a phase of a first of the plurality of distributed data signals is different from a phase of a second of the plurality of distributed data signals.

18. The device of claim 17, further configured to generate a first distributed clock signal and a second distributed clock signal based on the clock signal.

19. The device of claim 18, further comprising an output circuit configured to process the first distributed data signal in response to the first distributed clock signal, and process the second distributed data signal in response to the second distributed clock signal.

20. The device of claim 17, wherein a processing timing of the first distributed data signal and a processing timing of the second distributed data signal are different from each other.