TIMESTAMP ALIGNMENT ACROSS MULTIPLE COMPUTING NODES

• US 20200133330A1
• Filed: 12/24/2019
• Published: 04/30/2020
• Est. Priority Date: 03/05/2019
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: BORDOGNA, Mark, ROBINSON, Jonathan A.
• Granted Patent: US 11,693,448 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications
• CPC Class Codes: H04L 43/106 using time related information in packets, e.g. by adding timestamps
• CPC Class Codes: H04L 43/20 the monitoring system or the monitored elements being virtualised, abstracted or software-defined entities, e.g. SDN or NFV

Abstract

Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.

Claims

1. A method comprising:

determining a first offset of a time stamp counter (TSC) for a first central processing unit (CPU) node relative to a master timer, wherein the master timer is provided by a separate device;

determining a second offset of a TSC for a second CPU node relative to the master timer;

adjusting the TSC for a first CPU node based on the first offset; and

adjusting the TSC for a second CPU node based on the second offset.

2. The method of claim 1, wherein the separate device comprises one or more of:

a network interface controller, graphics processing unit card, or accelerator and the master timer is based on a network source.

3. The method of claim 1, wherein determining a first offset of a TSC for a first CPU node relative to a master timer comprises:

providing a copy of the TSC to the separate device;

determining a master time stamp when the copy of the TSC is received;

providing the master time stamp and the copy of the TSC to the first CPU node; and

the first CPU node determining the first offset based, at least, in part on the master time stamp and the copy of the TSC.

4. The method of claim 1, wherein determining a second offset of a TSC for the second CPU node relative to the master timer comprises:

providing a copy of the TSC to the separate device;

determining a master time stamp when the copy of the TSC is received;

providing the master time stamp and the copy of the TSC to the second CPU node; and

the second CPU node determining the first offset based, at least, in part on the master time stamp and the copy of the TSC.

5. The method of claim 1, wherein the first offset comprises a linear offset and the second offset comprises a linear offset.

6. The method of claim 1, wherein the first CPU node uses a first crystal oscillator to generate a TSC.

7. The method of claim 1, wherein the second CPU node uses a second crystal oscillator to generate a TSC.

8. An apparatus comprising:

a first central processing unit (CPU) node comprising a time stamp counter (TSC);

a second CPU node comprising a second TSC;

an interface to an accelerator device, wherein

the interface is to transfer a master time stamp for a first value of the TSC to the first CPU node and

the interface is to transfer a master time stamp for a second value of the TSC to the second CPU node.

9. The apparatus of claim 8, wherein:

the first CPU node is to provide the first value of the TSC to the accelerator device using the interface and

the second CPU node is to provide the second value of the TSC to the accelerator device using the interface.

10. The apparatus of claim 8, wherein:

the first CPU node is to determine a first offset for its time stamp based, at least, in part on the master time stamp for the first value of the TSC and

the second CPU node is to determine a second offset for its time stamp based, at least, in part on the master time stamp for the second value of the TSC.

11. The apparatus of claim 10, wherein the first CPU node and the second CPU node are to execute virtualized execution environments with time stamps that are synchronized based on the first and second offsets.

12. The apparatus of claim 8, wherein the accelerator device comprises one or more of:

a network interface controller, graphics processing unit card, or accelerator and the accelerator comprises a master timer.

13. The apparatus of claim 8, comprising a host computer, a compute sled, a rack, or a data center.

14. The apparatus of claim 8, wherein the master time stamp is based on a network source.

15. The apparatus of claim 8, wherein the master time stamp is based on one or more of:

an Ethernet port time stamp based on IEEE 1588 or a global positioning system (GPS) signal.

16. The apparatus of claim 8, wherein the accelerator device comprises a network interface that provides the master time stamp and the master time stamp is based on a network source.

17. The apparatus of claim 8, wherein the first CPU node is to use a first crystal oscillator to generate a TSC.

18. The apparatus of claim 8, wherein the second CPU node is to use a second crystal oscillator to generate a TSC.

19. A network interface comprising:

a timer source to provide a network-based timer value, wherein the timer source is based on signals received from a network;

a precision time measurement (PTM) device to receive a timer value from a first central processing unit (CPU) node; and

a second precision time measurement (PTM) device to receive a second timer value from a second central processing unit (CPU) node, wherein;

the PTM is to store a network-based timer value from the timer source associated with receipt of the timer value from the first CPU and provide a pair of the network-based timer value from the timer source associated with the timer value from the first CPU to the first CPU and

the second PTM is to store a network-based timer value from the timer source associated with receipt of the second timer value from the second CPU and provide a pair of the network-based timer value from the timer source associated with the timer value from the first CPU to the second CPU.

20. The network interface of claim 19, wherein the network-based timer value is based on one or more of:

an Ethernet port time stamp based on IEEE 1588 or a global positioning system (GPS) signal.