MACHINE INTELLIGENCE PERFORMANCE BOOST WITH ENERGY RESERVOIR

• US 20200133360A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sadowski, Greg
• Granted Patent: US 11,119,549 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

Control of power supplied to a machine intelligence (MI) processor is provided with an energy reservoir and power switching circuitry coupled to a power supply, the energy reservoir, and to power delivery circuitry of the MI processor. Control circuitry directs the power switching circuitry to charge the energy reservoir from the power supply or discharge the energy reservoir to the MI processor based on MI state information obtained from the MI processor. Processes for charging and discharging such an energy reservoir are provided. Processes for analyzing state information of the MI processor and configuring the control circuitry are also provided.

Claims

1. A circuit adapted to receive power from a power supply, the circuit comprising:

and a machine intelligence (MI) processor;

an energy reservoir;

power switching circuitry adapted to be coupled to the power supply, the energy reservoir, and to power delivery circuitry of the MI processor; and

control circuitry operable to direct the power switching circuitry to charge the energy reservoir from the power supply or discharge the energy reservoir to the MI processor based on MI state information obtained from the MI processor.

2. The power controller circuit of claim 1, in which the MI state information comprises information indicating whether a kernel implementing a neural network layer is active.

3. The power controller circuit of claim 1, in which the MI state information comprises information indicating whether circuitry implementing neural network calculations is operating.

4. The power controller circuit of claim 1, in which the MI state information comprises information indicating whether the MI processor is loading data from memory to inputs of a neural network.

5. The power controller circuit of claim 1, in which the control circuitry is further operable to signal the MI processor to increase a clock rate of MI calculation circuitry.

6. The power controller circuit of claim 1, in which the MI processor is implemented as a monolithic semiconductor chip.

7. A method comprising:

receiving state information from an integrated circuit configured to perform machine intelligence (MI) operations;

from the state information, determining a first condition exists in the integrated circuit, and in response directing power from a power supply to an energy reservoir; and

from the state information, determining a second condition exists in the integrated circuit, and in response directing power from the energy reservoir to the integrated circuit.

8. The method of claim 7, in which the state information includes information indicating whether a processor kernel is invoked to operate a neural network.

9. The method of claim 8, which the state information includes an indicator of a number of processor kernels invoked to operate the neural network.

10. The method of claim 7, in which the integrated circuit includes a massively parallel single instruction multiple data (SIMD) computation engine programmed to operate a neural network.

11. The method of claim 7, in which the state information comprises information indicating whether the integrated circuit is loading data from memory to inputs of a neural network.

12. The method of claim 7, in which the state information comprises information indicating that MI calculation circuitry of the integrated circuit is entering an active phase.

13. The method of claim 7, further comprising:

detecting periods of power requirements significantly below a capacity of the power supply;

in response, configuring state information for an energy reservoir controller to identify the first condition;

detecting periods of power usage at or near the capacity of the power supply; and

in response, configuring state information for the energy reservoir controller to identify the second condition.

14. The method of claim 7, further comprising directing power from the energy reservoir to an additional integrated circuit.

15. A system adapted to receive power from a power supply, the system comprising:

a semiconductor device configured for operating a machine intelligence (MI) processor, and including power terminals adapted to be coupled to positive and negative terminals of the power supply;

an energy reservoir is adapted to be coupled to the power supply positive and negative terminals and the power terminals of the semiconductor device; and

an energy reservoir controller is adapted to be coupled to the power supply, the energy reservoir, and to power delivery circuitry of the semiconductor device, the energy reservoir controller operable to direct power to charge the energy reservoir from the power supply or discharge the energy reservoir to the semiconductor device based on state information associated with the semiconductor device.

16. The system of claim 15, in which the state information comprises an indicator that a kernel of the semiconductor device is invoked to operate a neural network.

17. The system of claim 15, in which the state information comprises an indicator that the semiconductor device is loading data from memory to inputs of a neural network.

18. The system of claim 15, in which the semiconductor device is adapted to use more power than a maximum power of the power supply when the energy reservoir is discharged to the semiconductor device.

19. The system of claim 15, in which the energy reservoir controller is further operable to recognize a power usage pattern of the semiconductor device based on the state information.

20. The system of claim 15, in which the semiconductor device includes a massively parallel single instruction multiple data (SIMD) computation engine programmed to operate a neural network.