PAGE FRAME SECURITY

• US 20200133490A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leitao, Breno H., De Lima Junior, Juscelino Candido, Seo, Carlos Eduardo
• Granted Patent: US 11,086,517 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

Memory management that includes allocating physical memory having an append-only permission associated therewith to requesting user space applications is described. If a page frame is append-only, then data written to the page frame cannot be overwritten. Rather, any new data written to an append-only page frame must be written beginning at the next available write location within the page frame. An MMU determines whether a write request is requesting an append-only page frame, in which case, the MMU reserves the append-only page frame for the write request and consults a corresponding entry in a page table append to determine whether an offset associated with the write request is larger than a stored value in the entry that indicates the next available write location in the page frame. If so, the write request is executed and the data is written to the page frame beginning at the next available write location.

Claims

1. A computer-implemented method for memory management, the method comprising:

receiving, at a memory management unit (MMU), a write instruction;

determining, by the MMU, that an append flag associated with the write instruction is set;

reserving, by the MMU, a particular block of a physical memory for the write instruction;

determining, by the MMU, that an offset of the write instruction is larger than a value indicative of a next available write location in the particular block of the physical memory; and

executing the write instruction at least in part by writing data to the particular block of the physical memory beginning at a write location corresponding to the offset of the write instruction.

2. The computer-implemented method of claim 1, wherein determining that the offset is larger than the value indicative of the next available write location comprises:

accessing, by the MMU, an append-only table containing a plurality of entries, wherein each entry in the append-only table corresponds to a respective block of the physical memory;

identifying, by the MMU, a particular entry of the plurality of entries that corresponds to the particular block of the physical memory, wherein the particular entry comprises the value indicative of the next available write location in the particular block of the physical memory.

3. The computer-implemented method of claim 2, wherein the value indicative of the next available write location is a pointer to a last location written to in the particular block of the physical memory or a pointer to a next available write location in the particular block of the physical memory.

4. The computer-implemented method of claim 1, wherein the particular block of the physical memory comprises a memory protection field that is set to indicate that existing data stored in the particular block of the physical memory cannot be modified and only new data can be appended to the existing data.

5. The computer-implemented method of claim 1, wherein the write instruction is a first write instruction and the particular block of the physical memory is a first block of the physical memory, the method further comprising:

receiving, at the MMU, a second write instruction;

determining, by the MMU, that an append flag associated with the second write instruction is not set;

executing the second write instruction at least in part by overwriting existing data stored in a second block of the physical memory with new data.

6. The computer-implemented method of claim 1, wherein the write instruction is a first write instruction, the method further comprising:

increasing the value indicative of the next available write location in the particular block of the physical memory based at least in part writing the data to the particular block of the physical memory;

receiving, at the MMU, a second write instruction;

determining, by the MMU, that an append flag associated with the second write instruction is set;

reserving, by the MMU, the particular block of the physical memory for the second write instruction;

determining, by the MMU, that an offset of the second write instruction is not larger than the updated value indicative of the next available write location in the particular block of the physical memory; and

generating, by the MMU, a page fault for the second write instruction.

7. The computer-implemented method of claim 1, wherein the particular block of the physical memory is a page frame, and wherein the value indicative of the next available write location is within a range of values from zero to a page size of the page frame.

8. A system for memory management, the system comprising:

physical memory storing computer-executable instructions;

at least one processor; and

a memory management unit (MMU) configured to handle memory access requests on behalf of the at least one processor, wherein the MMU is configured to access the physical memory and execute the computer-executable instructions to;

receive a write instruction;

determine that an append flag associated with the write instruction is set;

reserve a particular block of the physical memory for the write instruction;

determine that an offset of the write instruction is larger than a value indicative of a next available write location in the particular block of the physical memory; and

execute the write instruction at least in part by writing data to the particular block of the physical memory beginning at a write location corresponding to the offset of the write instruction.

9. The system of claim 8, wherein the MMU is configured to determine that the offset is larger than the value indicative of the next available write location by executing the computer-executable instructions to:

access an append-only table containing a plurality of entries, wherein each entry in the append-only table corresponds to a respective block of the physical memory;

identify a particular entry of the plurality of entries that corresponds to the particular block of the physical memory, wherein the particular entry comprises the value indicative of the next available write location in the particular block of the physical memory.

10. The system of claim 9, wherein the value indicative of the next available write location is a pointer to a last location written to in the particular block of the physical memory or a pointer to a next available write location in the particular block of the physical memory.

11. The system of claim 8, wherein the particular block of the physical memory comprises a memory protection field that is set to indicate that existing data stored in the particular block of the physical memory cannot be modified and only new data can be appended to the existing data.

12. The system of claim 8, wherein the write instruction is a first write instruction and the particular block of the physical memory is a first block of physical memory, and wherein the MMU is further configured to execute the computer-executable instructions to:

receive a second write instruction;

determine that an append flag associated with the second write instruction is not set;

execute the second write instruction at least in part by overwriting existing data stored in a second block of the physical memory with new data.

13. The system of claim 8, wherein the write instruction is a first write instruction, and wherein the MMU is further configured to execute the computer-executable instructions to:

increase the value indicative of the next available write location in the particular block of the physical memory based at least in part writing the data to the particular block of the physical memory;

receive a second write instruction;

determine that an append flag associated with the second write instruction is set;

reserve the particular block of the physical memory for the second write instruction;

determine that an offset of the second write instruction is not larger than the updated value indicative of the next available write location in the particular block of the physical memory; and

generate a page fault for the second write instruction.

14. The system of claim 8, wherein the particular block of the physical memory is a page frame, and wherein the value indicative of the next available write location is within a range of values from zero to a page size of the page frame.

15. A computer program product for memory management, the computer program product comprising a storage medium readable by a processing circuit, the storage medium storing instructions executable by the processing circuit to cause a method to be performed, the method comprising:

receiving, at a memory management unit (MMU), a write instruction;

determining, by the MMU, that an append flag associated with the write instruction is set;

reserving, by the MMU, a particular block of the physical memory for the write instruction;

determining, by the MMU, that an offset of the write instruction is larger than a value indicative of a next available write location in the particular block of the physical memory; and

executing the write instruction at least in part by writing data to the particular block of the physical memory beginning at a write location corresponding to the offset of the write instruction.

16. The computer program product of claim 15, wherein determining that the offset is larger than the value indicative of the next available write location comprises:

accessing, by the MMU, an append-only table containing a plurality of entries, wherein each entry in the append-only table corresponds to a respective block of physical memory;

identifying, by the MMU, a particular entry of the plurality of entries that corresponds to the particular block of the physical memory, wherein the particular entry comprises the value indicative of the next available write location in the particular block of the physical memory.

17. The computer program product of claim 16, wherein the value indicative of the next available write location is a pointer to a last location written to in the particular block of the physical memory or a pointer to a next available write location in the particular block of the physical memory.

18. The computer program product of claim 15, wherein the particular block of the physical memory comprises a memory protection field that is set to indicate that existing data stored in the particular block of the physical memory cannot be modified and only new data can be appended to the existing data.

19. The computer program product of claim 15, wherein the write instruction is a first write instruction and the particular block of the physical memory is a first block of physical memory, the method further comprising:

receiving, at the MMU, a second write instruction;

determining, by the MMU, that an append flag associated with the second write instruction is not set;

executing the second write instruction at least in part by overwriting existing data stored in a second block of the physical memory with new data.

20. The computer program product of claim 15, wherein the write instruction is a first write instruction, the method further comprising:

increasing the value indicative of the next available write location in the particular block of the physical memory based at least in part writing the data to the particular block of the physical memory;

receiving, at the MMU, a second write instruction;

determining, by the MMU, that an append flag associated with the second write instruction is set;

reserving, by the MMU, the particular block of the physical memory for the second write instruction;

determining, by the MMU, that an offset of the second write instruction is not larger than the updated value indicative of the next available write location in the particular block of the physical memory; and

generating, by the MMU, a page fault for the second write instruction.