MEMORY SYSTEM AND CONTROL METHOD THEREOF

• US 20200133496A1
• Filed: 12/30/2019
• Published: 04/30/2020
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: KITSUNAI, Kazuya, KANNO, Shinichi, YANO, Hirokuni, HIDA, Toshikatsu, YANO, Junji
• Granted Patent: US 11,287,975 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

Claims

1. (canceled)

2. A memory system comprising:

an interface configured to receive data;

a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for an erase operation; and

a controller electrically connected to the nonvolatile memory and configured to;

copy first data from a first block to a second block, the number of erase operations performed on the second block being larger than the number of erase operations performed on the first block; and

when the copying is not performed, write second data to a third block, the second data being data that is received through the interface and has not been stored in the nonvolatile memory.

3. The memory system according to claim 2, wherein

the interface is configured to be connected with a host,

the first data is valid data,

the second block does not store valid data prior to the copying of the first data, and

the third block does not store valid data prior to the writing of the second data, wherein

the valid data is data stored in a block to which a logical address designated by the host is allocated.

4. The memory system according to claim 2, wherein

the interface is configured to be connected with a host, and

the controller is further configured to maintain an address conversion table to associate a logical address designated by the host with an identifier of each of the plurality of blocks, wherein,

in the address conversion table,

the identifier of the first block is associated with a logical address designated by the host prior to the copying of the first data,

the identifier of the second block is not associated with a logical address designated by the host prior to the copying of the first data, and

the identifier of the third block is not associated with a logical address designated by the host prior to the writing of the second data.

5. The memory system according to claim 2, wherein

prior to the writing of the second data, the number of erase operations performed on the third block is smallest among the numbers of erase operations performed on empty blocks among the plurality of blocks, each of the empty blocks being a block to which a logical address designated by a host is not allocated.

6. The memory system according to claim 2, wherein

the controller is configured to perform the copying when a difference between the number of erase operations performed on the first block and the number of erase operations performed on the second block is larger than a first threshold.

7. The memory system according to claim 2, wherein

the controller is configured to perform the copying when the number of erase operations performed on a fourth block is larger than a second threshold.

8. The memory system according to claim 2, wherein

the controller is further configured to maintain a block management table, wherein

the controller is configured to manage, in the block management table, the first block as an empty block after the copying of the first data, the empty block being a block to which a logical address designated by a host is not allocated.

9. The memory system according to claim 8, wherein

the controller is further configured to perform an erase operation on the first block after the copying of the first data.

10. A memory system comprising:

a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for an erase operation; and

a controller electrically connected to the nonvolatile memory and configured to,

when the number of erase operations performed on a first block is larger than a first threshold,

copy first data from a second block to a third block, the number of erase operations performed on the third block being larger than the number of erase operations performed on the second block.

11. The memory system according to claim 10, wherein

the controller is further configured to return the second block, which has become to store obsolete data, to a free block pool.

12. The memory system according to claim 11, wherein

the controller is further configured to perform an erase operation on the second block.

13. The memory system according to claim 10, wherein

the controller is further configured to employ a scheme of block mapping to map a logical address designated by a host to an identifier of each of the plurality of blocks, wherein,

in the scheme,

the identifier of the second block is mapped to a logical address designated by the host, and

the identifier of the third block is not mapped to a logical address designated by the host.

14. The memory system according to claim 10, wherein

the controller is further configured to write second data to a fourth block, the number of erase operations performed on the fourth block being smallest among the numbers of erase operations performed on blocks managed in a free block pool.

15. The memory system according to claim 14, wherein

the controller is configured to:

select the second block from among a first number of blocks; and

select the fourth block from among a second number of blocks, the first number being larger than the second number.

16. A memory system comprising:

a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for an erase operation; and

a controller electrically connected to the nonvolatile memory and configured to perform a leveling process considering degree of burden of a frequently data rewritten block, wherein

the leveling process including;

reading data from a first block to which a first logical address designated by a host is allocated;

writing the data read from the first block to a second block of which data is erased;

releasing the first logical address from the first block; and

allocating the first logical address to the second block.

17. A memory system comprising:

an interface configured to receive data;

a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for an erase operation; and

a controller electrically connected to the nonvolatile memory and configured to write first data to a first block, the first data being data that is received through the interface and has not been stored in the nonvolatile memory, wherein

the number of erase operations performed on the first block is smallest among the numbers of erase operations performed on empty blocks.

18. The memory system according to claim 17, wherein

the controller is further configured to copy second data from a second block to a third block, the number of erase operations performed on the third block being larger than the number of erase operations performed on the second block.

19. The memory system according to claim 18, wherein

the controller is configured to perform the copying when the first data is not written to the first block.

20. The memory system according to claim 18, wherein

the controller is configured to perform the copying when the number of erase operations performed on a fourth block is larger than a first threshold.

21. The memory system according to claim 18, wherein

each of the empty blocks is a block to which a logical address designated by a host is not allocated.