MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE MEMORY DEVICE, AND METHOD OF OPERATING THE MEMORY SYSTEM

• US 20200133501A1
• Filed: 04/26/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Hyun Woo, KIM, Young Gyun
• Granted Patent: US 10,969,987 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents

Abstract

A memory system includes: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to perform a read operation on a selected memory block among the plurality of memory blocks and a backup program operation on a backup block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit to backup data of logical pages included in the selected memory block in the backup block, when a read count of a selected physical page of the selected memory block is equal to or larger than a set value in the read operation on the selected memory block.

Claims

1. A memory device comprising:

a memory cell array including a plurality of memory blocks;

a peripheral circuit configured to perform a read operation on a selected memory block among the plurality of memory blocks, and a backup program operation on a backup block among the plurality of memory blocks; and

a control circuit configured to control the peripheral circuit to backup data of weak logical pages included in the selected memory block in the backup block when a read count of a selected physical page of the selected memory block is equal to or larger than a set value in the read operation on the selected memory block.

2. The memory device of claim 1,

wherein the plurality of memory blocks include a plurality of physical pages, and each of the plurality of physical pages includes a plurality of logical pages,

wherein the plurality of logical pages are a Least Significant Bit (LSB) page, a Central Significant Bit (CSB) page, and a Most Significant Bit (MSB) page, and the weak logical page is the MSB page weak to a read disturb.

3. The memory device of claim 2, wherein the peripheral circuit stores, in the backup operation, data of the weak logical page included in the selected memory block in one selected physical page among the plurality of physical pages of the backup block.

4. A memory system comprising:

a memory device including a plurality of memory blocks, the memory device reading and outputting data stored in a selected page of a selected memory block among the plurality of memory blocks in a read operation; and

a controller configured to control the memory device to perform the read operation in response to a request from a host,

wherein the controller controls, when a read count of the selected page is equal to or larger than a set value in the read operation, the memory device to perform a backup operation of storing data of weak logical pages included in the selected memory block including the selected page in a backup block among the plurality of memory blocks.

5. The memory system of claim 4, wherein the controller includes:

a processor configured to generate a command queue for controlling the memory device in the request from the host; and

an Error Correction Code (ECC) circuit configured to perform an ECC operation on data received from the memory device in the read operation.

6. The memory system of claim 5, wherein, when it is determined that the ECC operation has passed in the read operation and the read count of the selected page is equal to or larger than the set value, the processor generates the command queue corresponding to the backup operation of the weak logical pages of the selected memory block.

7. The memory system of claim 5, wherein, when it is determined that the ECC operation has passed in the read operation, the read count of the selected page is equal to or larger than the set value, and a backup operation history of the memory block does not exist, the processor generates the command queue corresponding to the backup operation of the weak logical pages of the selected memory block.

8. The memory system of claim 4,

wherein the plurality of memory blocks include a plurality of physical pages, and each of the plurality of physical pages includes a plurality of logical pages,

wherein the plurality of logical pages are a Least Significant Bit (LSB) page, a Central Significant Bit (CSB) page, and a Most Significant Bit (MSB) page, and the weak logical page is the MSB page weak to a read disturb.

9. The memory system of claim 8, wherein, in the backup operation, the memory device stores data of the weak logical page included in the selected memory block in one selected physical page among the plurality of physical pages of the backup block.

10. The memory system of claim 5,

wherein, when it is determined that the ECC operation has failed in the read operation, the controller controls the memory device to perform a hard decoding operation and a soft decoding operation,

wherein, when it is determined that the soft decoding operation has passed and the selected page is not the weak logical page, the controller controls the memory device to perform a read reclaim operation.

11. The memory system of claim 10, wherein, when it is determined that the soft decoding operation has passed and the selected page is the weak logical page, the controller updates an address of the selected page to an address at which the backup operation has been performed.

12. A method of operating the memory system, the method comprising:

performing a read operation on a selected page included in a selected memory block among a plurality of memory blocks and an Error Correction Code (ECC) operation on read data;

comparing a read count of the selected page with a set value, when it is determined that the ECC operation has passed; and

performing a backup operation of weak logical pages included in the selected memory block, when the read count is equal to or larger than the set value.

13. The method of claim 12,

further comprising determining a history in which the backup operation on the selected memory block has been performed, when the read count is equal to or larger than the set value,

wherein the backup operation on the selected memory block is performed when the history in which the backup operation has been performed does not exist.

14. The method of claim 12,

wherein the plurality of memory blocks include a plurality of physical pages, and each of the plurality of physical pages includes a plurality of logical pages,

wherein the plurality of logical pages are a Least Significant Bit (LSB) page, a Central Significant Bit (CSB) page, and a Most Significant Bit (MSB) page, and the weak logical page is the MSB page weak to a read disturb.

15. The method of claim 14, wherein the backup operation stores the data stored in each of the weak logical pages in a plurality of pages of the backup block, using a Single Level Cell (SLC) scheme.

16. The method of claim 14, wherein data of at least one weak logical page among the weak logical pages is stored, in the backup operation, in one page among the plurality of pages of the backup block.

17. The method of claim 14, further comprising performing a hard decoding operation and a soft decoding operation on the selected page, when it is determined that the ECC operation has failed.

18. The method of claim 17, wherein the operations are re-performed from the comparing of the read count with the set value, when it is determined that the hard decoding operation has passed.

19. The method of claim 17, further comprising updating an address of the selected page as an address at which the backup operation has been performed, when it is determined that the soft decoding operation has passed and the selected page is the weak logical page.

20. The method of claim 17, further comprising performing a read reclaim operation on the selected page, when it is determined that the soft decoding operation has passed and the selected page is not the weak logical page.