SYSTEM ON CHIP PERFORMING TRAINING OF DUTY CYCLE OF WRITE CLOCK USING MODE REGISTER WRITE COMMAND, OPERATING METHOD OF SYSTEM ON CHIP, ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP

• US 20200133505A1
• Filed: 07/02/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, YONGSEOB
• Granted Patent: US 11,061,577 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A system on chip includes a first clock generator that generates a first clock to be sent to a memory device, a second clock generator that generates a second clock to be sent to the memory device, a command and address generator that generate a code for adjusting a duty cycle of a third clock generated within the memory device based on the second clock and generates a command for storing the code to mode registers of the memory device, the third clock being used for a data input/output of the memory device, a data receiver that receives a data strobe signal and a data input/output signal output from the memory device receiving the command and the code synchronized with the first clock, and a training circuit that calculates a plurality of valid window margins for the code based on the data strobe signal and the data input/output signal.

Claims

1. A system on chip comprising:

a first clock generator configured to generate a first clock to be sent to a memory device;

a second clock generator configured to generate a second clock to be sent to the memory device;

a command and address generator configured to generate a code for adjusting a duty cycle of a third clock generated within the memory device based on the second clock, and generate a command for storing the code to mode registers of the memory device, the third clock being used for a data input/output of the memory device;

a data receiver configured to receive a data strobe signal and a data input/output signal output from the memory device receiving the command and the code synchronized with the first clock; and

a training circuit configured to calculate a plurality of valid window margins for the code based on the data strobe signal and the data input/output signal.

2. The system on chip of claim 1, wherein the command and address generator is configured to repeatedly generate the command and the code, and

wherein a plurality of values of the code repeatedly generated by the command and address generator correspond to the plurality of valid window margins, respectively.

3. The system on chip of claim 1, wherein the command and address generator is further configured to generate an address indicating the mode registers of the memory device, and send the address synchronized with the first clock to the memory device.

4. The system on chip of claim 1, wherein a duty cycle adjuster of the memory device is configured to adjust the duty cycle of the third clock depending on a value of the code stored in the mode registers.

5. The system on chip of claim 1, wherein the training circuit is configured to find a target value of the code, which corresponds to a maximum valid window margin of the plurality of valid window margins, from among a plurality of values of the code, and

wherein the command and address generator is configured to send, to the memory device, the target value of the code and a command for storing the target value of the code to the mode registers of the memory device.

6. The system on chip of claim 1, wherein a frequency of the second clock is higher than a frequency of the first clock.

7. The system on chip of claim 1, wherein a first value of the code is changed to a second value by the command and address generator,

wherein a duty cycle of the second clock when the first value of the code is sent to the memory device is identical to a duty cycle of the second clock when the second value of the code is sent to the memory device, and

wherein a duty cycle of the third clock adjusted according to the first value of the code is different from a duty cycle of the third clock adjusted according to the second value of the code.

8. The system on chip of claim 1, wherein, when a value of the code is changed, the command and address generator sends a write command and test data to the memory device.

9. The system on chip of claim 1, wherein the second clock generator comprises a duty cycle adjuster configured to adjust a duty cycle of the second clock to be output to the memory device.

10. The system on chip of claim 1, wherein the memory device is a low power double data rate 5 synchronous dynamic random access memory (LPDDR5 SDRAM) device, and

wherein the command is a mode register write command.

11. An operating method of a system on chip connected with a memory device, the method comprising:

changing a code to be sent to the memory device in synchronization with a first clock, the code being used to adjust a duty cycle of a third clock which is generated within the memory device based on a second clock generated from the system on chip, and is used for a data input/output of the memory device;

calculating a plurality of valid window margins for the code based on a data strobe signal and a data input/output signal output from the memory device receiving the code; and

sending a target value of the code corresponding to a maximum valid window margin of the plurality of valid window margins to the memory device.

12. The method of claim 11, wherein the changing the code comprises:

generating a command for writing a value of the code to mode registers of the memory device;

generating an address indicating the mode registers in which the value of the code is to be stored; and

sending the command, the address, and the value of the code synchronized with the first clock to the memory device.

13. The method of claim 11, wherein the calculating the plurality of valid window margins for the code comprises:

generating a write command for writing test data to the memory device and sending the write command to the memory device; and

generating a read command for reading the test data stored in the memory device by the write command and sending the read command to the memory device.

14. The method of claim 13, wherein the data strobe signal and the data input/output signal are output from the memory device operating based on the third clock.

15. The method of claim 14, wherein the sending the write command to the memory device comprises:

sending the test data to the memory device through command and address transmission paths.

16. An electronic device comprising:

a system on chip configured to generate a first clock and a second clock having a frequency higher than a frequency of the first clock; and

a memory device synchronized with the first clock and the second clock output from the system on chip,

wherein the system on chip is further configured to;

generate a command and a code synchronized with the first clock; and

train a duty cycle of a third clock which is generated within the memory device based on the second clock and is used for a data input/output of the memory device, by sending the command and the code to the memory device.

17. The electronic device of claim 16, wherein a first data input/output being the data input/output is performed through first paths between the system on chip and the memory device,

wherein a second data input/output of the memory device is performed through second paths between the system on chip and the memory device,

wherein the system on chip is configured to further generate a fourth clock having a frequency identical to the frequency of the second clock, and

wherein the system on chip is further configured to train a duty cycle of a fifth clock which is generated within the memory device based on the fourth clock and is used for the second data input/output of the memory device, by sending the command and the code to the memory device.

18. The electronic device of claim 16, wherein the system on chip is further configured to:

calculate a plurality of valid window margins for the code based on a data strobe signal and a data input/output signal output from the memory device; and

send a target value of the code corresponding to a maximum valid window margin among the plurality of valid window margins and the command to the memory device.

19. The electronic device of claim 18, wherein the command is a mode register write command, and

wherein the system on chip is further configured to send a write command and a read command synchronized with the first clock to the memory device after sending the code to the memory device, and receive the data strobe signal and the data input/output signal from the memory device based on the read command.

20. The electronic device of claim 19, wherein

the memory device is a low power double data rate 5 synchronous dynamic random access memory (LPDDR5 SDRAM) device, and

wherein the target value of the code is stored to mode registers of the memory device.