×

TOLERATING MEMORY STACK FAILURES IN MULTI-STACK SYSTEMS

  • US 20200133518A1
  • Filed: 10/31/2018
  • Published: 04/30/2020
  • Est. Priority Date: 10/31/2018
  • Status: Active Grant
First Claim
Patent Images

1. A memory system, comprising:

  • a random-access memory including a plurality of memory stacks, each including a plurality of stacked random-access memory integrated circuit dies;

    a memory controller coupled to said random-access memory and operable to;

    receive a block of data for writing to the memory stacks;

    divide the block of data into a plurality of sub-blocks;

    create a reliability sub-block based on the plurality of sub-blocks;

    cause the plurality of sub-blocks and the reliability sub-block each to be written to a different one of the memory stacks;

    cause the plurality of sub-blocks to be read from the plurality of memory stacks and detect an error therein indicating a failure within one of the memory stacks; and

    in response to detecting the error, recover correct data based on the reliability sub-block.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×