SYSTEMS AND METHODS FOR DATA PATH POWER SAVINGS IN DDR5 MEMORY DEVICES

• US 20200133525A1
• Filed: 12/30/2019
• Published: 04/30/2020
• Est. Priority Date: 08/31/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kandikonda, Ravi Kiran
• Granted Patent: US 11,209,994 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory device includes a data path having a data bus. The memory derive further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.

Claims

1. A memory device, comprising:

a data path comprising a data bus;

a first one-hot communications interface communicatively coupled to the data bus;

a second one-hot communications interface communicatively coupled to the data bus;

at least one memory bank; and

an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank, wherein the first one-hot communications interface comprises a pumping parallelizer circuitry configured to convert the first data pattern into one or more phase-separated nibbles of data.

2. The memory device of claim 1, wherein the one or more phase-separated nibbles of data comprise a clock-phased data that has been partitioned.

3. The memory device of claim 1, wherein the first one-hot communications interface comprises a decoder circuitry configured to receive the one or more phase-separated nibbles of data and configured to decode the one or more phase-separated nibbles of data into the one-hot signals.

4. The memory device of claim 3, wherein the data bus comprises a 16-bit data bus, wherein the pumping parallelizer circuitry comprises a quad pumping parallelizer circuitry configured to convert the first data pattern into 4 phase-separated nibbles of data, and wherein each of the 4 phase-separated nibbles of data comprises 4 bits.

5. The memory device of claim 1, wherein the second one-hot communications interface comprises an encoder circuit configured to convert the one-hot signals into the first data pattern.

6. The memory device of claim 1, wherein the data path comprises a first data junction;

a second data junction communicatively coupled to the at least one memory bank; and

a repeater, wherein the first and second data junctions are communicatively coupled to each other via the repeater, and wherein the one-hot signals are configured to be transmitted from the first one-hot communications interface to the first data junction via the data bus, then to the repeater, and then to the second data junction via the repeater be stored into the at least one memory bank.

7. The memory device of claim 1, wherein the second one-hot communications interface is configured to convert a second data pattern stored in the at least one memory into second one-hot signals transmitted to the first one-hot communications interface, and wherein the first one-hot communications interface is configured to convert the second one-hot signals into the second data pattern to be communicated to an external system via the I/O interface.

8. The memory device of claim 7, wherein the second one-hot communications interface comprises a pumping parallelizer circuitry configured to convert the second data pattern into one or more phase-separated nibbles of data, a decoder circuitry configured to receive the one or more phase-separated nibbles of data and configured to decode the one or more phase-separated nibbles of data into the second one-hot signals.

9. The memory device of claim 1, comprising a double data rate type five (DDR5) memory device having the data path, the first one-hot communications interface, the second one-hot communications interface, the at least one memory bank, and the I/O interface.

20. The memory device of claim 1, comprising a double data rate type five (DDR5) memory device having the first one-hot communications interface.

10. A method, comprising:

receiving a write command at a memory device;

converting, via the memory device, a first data pattern to be written in a memory bank of the memory device into first one-hot signals based on the write command;

transmitting, via a data bus of the memory device, the first one-hot signals to a first one-hot communications interface of the memory device;

converting, via the first one-hot communications interface, the first one-hot signals into the first data pattern, wherein converting via the memory device, the first data pattern comprises deriving a plurality of nibbles based on the first data pattern by partitioning the first data pattern; and

saving the first data pattern in the memory bank.

11. The method of claim 10, wherein partitioning the first data patter comprises determining a number of bits in each nibble of the plurality of nibbles based on a data bus width.

12. The method of claim 11, wherein converting via the memory device, the first data pattern comprises decoding the plurality of nibbles into the first one-hot signals based on a one-hot signal decoding table.

13. The method of claim 10, wherein transmitting, via the data bus of the memory device, the first one-hot signals comprises the first one-hot signals traversing a data junction of the memory device, a repeater of the memory device, or a combination thereof.

14. The method of claim 10, comprising:

receiving a read command at the memory device;

converting, via the memory device, a second data pattern to be read from the memory bank of the memory device into second one-hot signals based on the read command;

transmitting, via the data bus of the memory device, the second one-hot signals from first one-hot communications interface of the memory device;

converting, via a second one-hot communications interface, the one-hot signals into the second data pattern; and

providing the second data pattern to an Input/Output (DQ) pad of the memory device.

15. The method of claim 14, wherein converting, via the second one-hot communications interface, the one-hot signals into the second data pattern comprises decoding the second one-hot signals via a one-hot signal decoder circuitry.

16. A memory device, comprising:

a first one-hot communications interface comprising;

a first pumping parallelizer circuitry configured to convert a first data pattern into one or more phase-separated nibbles of data by partitioning the first data pattern; and

a first decoder circuitry configured to receive the one or more phase-separated nibbles of data and configured to decode the one or more phase-separated nibbles of data into first one-hot signals, wherein the first one-hot communications interface is configured to transmit the first one-hot signals via a data bus for storage of the first data pattern in a memory bank of the memory device.

17. The memory device of claim 16, comprising:

a second one-hot communications interface comprising a first encoder circuit configured to convert the first one-hot signals into the first data pattern for storage of the first data pattern in the memory bank.

18. The memory device of claim 17, wherein the second one-hot communications interface comprises:

a second pumping parallelizer circuitry configured to convert a second data pattern stored in the memory bank into second one or more phase-separated nibbles of data; and

a second decoder circuitry configured to receive the second one or more phase-separated nibbles of data and configured to decode the second one or more phase-separated nibbles of data into second one-hot signals, wherein the second one-hot communications interface is configured to transmit the second one-hot signals via the data bus to an Input/Output (DQ) pad of the memory device.

19. The memory device of claim 18, wherein the first one-hot”

communications interface comprises a second encoder circuit configured to convert the second one-hot signals into the second data pattern for transmission of the second data pattern to the DQ pad.