SYSTEM ON CHIP PERFORMING A PLURALITY OF TRAININGS AT THE SAME TIME, OPERATING METHOD OF SYSTEM ON CHIP, ELECTRONIC DEVICE INCLUDING SYSTEM ON CHIP
First Claim
1. A system on chip comprising:
- a clock generator configured to adjust a duty cycle of a clock to be output to a memory device depending on a first code;
a reference voltage generator configured to adjust a first level of a first reference voltage used to determine a first data input/output signal output from the memory device depending on a second code;
a data receiver configured to align a first data strobe signal and the first data input/output signal output from the memory device, when one of the first code and the second code is changed; and
a processor configured to calculate a plurality of read valid window margins for a plurality of combinations of the first code and the second code based on the first data strobe signal and the first data input/output signal.
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Accused Products
Abstract
A system on chip includes a clock generator that adjusts a duty cycle of a clock to be output to a memory device depending on a first code, a reference voltage generator that adjusts a level of a reference voltage used to determine a first data input/output signal output from the memory device depending on a second code, a data receiver that aligns a first data strobe signal and the first data input/output signal output from the memory device, when one of the first code and the second code is changed, and a training circuit that calculates a plurality of read valid window margins for a plurality of combinations of the first code and the second code based on the first data strobe signal and the first data input/output signal.
24 Citations
20 Claims
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1. A system on chip comprising:
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a clock generator configured to adjust a duty cycle of a clock to be output to a memory device depending on a first code; a reference voltage generator configured to adjust a first level of a first reference voltage used to determine a first data input/output signal output from the memory device depending on a second code; a data receiver configured to align a first data strobe signal and the first data input/output signal output from the memory device, when one of the first code and the second code is changed; and a processor configured to calculate a plurality of read valid window margins for a plurality of combinations of the first code and the second code based on the first data strobe signal and the first data input/output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An operating method of a system on chip connected with a memory device, the method comprising:
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changing one of a first code for adjusting a duty cycle of a clock to be provided to the memory device and a second code for adjusting a first level of a first reference voltage of the system on chip used to determine a first data input/output signal output from the memory device; aligning a first data strobe signal and the first data input/output signal output from the memory device; calculating a plurality of read valid window margins for a plurality of combinations, each one of the plurality of combinations being a pair of one of values of the first code and one of values of the second code, based on the first data strobe signal and the first data input/output signal; and setting the duty cycle of the clock and the first level of the first reference voltage of the system on chip, respectively, based on a first target value of the first code and a second target value of the second code corresponding to a maximum read valid window margin of the plurality of read valid window margins. - View Dependent Claims (12, 13, 14, 15)
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16. An electronic device comprising:
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a system on chip configured to generate a clock; and a memory device synchronized with an output from the clock, wherein the system on chip is further configured to simultaneously perform a first training of a duty cycle of the clock adjusted according to a first code, a second training of a first level of a first reference voltage of the system on chip which is adjusted according to a second code and is used to determine a first data input/output signal output from the memory device, and a third training of a first skew between a first data strobe signal and the first data input/output signal output from the memory device. - View Dependent Claims (17, 18, 19, 20)
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Specification