MEMORY SYSTEM FOR MANAGING FREE PAGES BASED ON REAL TIME CLOCK AND OPERATING METHOD THEREOF

• US 20200133573A1
• Filed: 06/10/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: BYUN, Eu-Joon
• Granted Patent: US 10,908,843 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1056 Simplification
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A memory system includes a memory device comprising a plurality of memory blocks; and a controller suitable for controlling the memory device, wherein the controller comprises a real time clock (RTC) management circuitry suitable for generating a sudden power-off (SPO) occurrence cycle using first and second RTC values when a first SPO occurs, and then comparing the SPO occurrence cycle to a threshold value to determine whether to delay dummy page generation; and a dummy page generation circuitry suitable for generating a dummy page using one or more free pages or an incomplete program page, excluding valid pages, from a memory block, among the plurality of memory blocks, according to the determination result of the RTC manager, the incomplete program page indicating a page in which a program operation is interrupted due to an SPO.

Claims

1. A memory system comprising:

a memory device comprising a plurality of memory blocks; and

a controller suitable for controlling the memory device,

wherein the controller comprises;

a real time clock (RTC) management circuitry suitable for generating a sudden power-off (SPO) occurrence cycle using first and second RTC values when a first SPO occurs, and then comparing the SPO occurrence cycle to a threshold value to determine whether to delay dummy page generation; and

a dummy page generation circuitry suitable for generating a dummy page using one or more free pages or an incomplete program page, excluding valid pages, from a memory block, among the plurality of memory blocks, according to the determination result of the RTC manager, the incomplete program page indicating a page in which a program operation is interrupted due to an SPO.

2. The memory system of claim 1, wherein the first RTC value indicates an SPO occurrence time, which is generated before the first SPO, the first RTC value being stored in a list that stores one or more RTC values, each of which indicates a corresponding SPO generation time and is generated before a corresponding SPO occurs.

3. The memory system of claim 1, wherein the RTC management circuitry comprises a first RTC load circuitry suitable for deciding whether operations are to be performed in a first or second mode, depending on a result obtained by determining whether the first RTC value is loaded from a list.

4. The memory system of claim 3, wherein the first RTC load circuitry decides the first mode of operation when the first RTC value is not present in the list, and decides the second mode of operation when the first RTC value is present in the list.

5. The memory system of claim 4, further comprising a second RTC generation circuitry suitable for receiving a booting time value from a host in the case that the memory system is powered on and generating a second RTC value indicating a first SPO occurrence time using the booting time value, when the first mode of operation is decided.

6. The memory system of claim 4, further comprising:

a second RTC generation circuitry;

a comparison circuitry; and

a time delay circuitry;

wherein when the second mode of operation is decided

the second RTC generation circuitry receives a booting time value from a host when the memory system is powered on, and generates a second RTC value indicating a first SPO occurrence time using the booting time value;

the comparison circuitry compares the SPO occurrence cycle to a threshold value and determines whether a second SPO is likely to occur, the SPO occurrence cycle being calculated through a difference between the first RTC value received through the first RTC load circuitry and the second RTC value generated through the second RTC generation circuitry; and

the time delay circuitry delays a dummy page generation time by a first delay time, when the comparison result between the SPO occurrence cycle and the threshold value indicates that the SPO occurrence cycle is less than the threshold value.

7. The memory system of claim 6, wherein, when the comparison result between the SPO occurrence cycle and the threshold value indicates that the SPO occurrence cycle is greater than the threshold value, the dummy page is generated through the dummy page generator.

8. An operating method of a memory system which includes a memory device including a plurality of memory blocks and a controller suitable for controlling the memory device, the operating method comprising:

generating a sudden power-off (SPO) occurrence cycle using first and second real time clock (RTC) values when a first SPO occurs, and comparing the SPO occurrence cycle to a threshold value to determine whether to delay dummy page generation; and

generating a dummy page using one or more free pages or an incomplete program page, excluding valid pages, from a memory block, among the plurality of memory blocks, according to the result of the determining of whether to delay dummy page generation, the incomplete program page indicating a page in which a program operation is interrupted due to an SPO.

9. The operating method of claim 8, wherein the first RTC value indicates an SPO occurrence time, which is generated before the first SPO, the first RTC value being stored in a list that stores one or more RTC values, each of which indicates a corresponding SPO generation time and is generated before a corresponding SPO occurs.

10. The operating method of claim 8, further comprising deciding whether operations are to be performed in a first or second mode, depending on whether the first RTC value is loaded from a list.

11. The operating method of claim 10, wherein the first mode of operation indicates a case in which the first RTC value is not present in the list.

12. The operating method of claim 11, wherein the first mode comprises receiving a booting time value from a host when the memory system is powered on, and generating a second RTC value indicating a first SPO occurrence time using the booting time value.

13. The operating method of claim 10, wherein the second mode of operation indicates that the first RTC value is present in the list.

14. The operating method of claim 13, wherein the second mode of operation comprises:

receiving a booting time value from the host when the memory system is powered on, and generating a second RTC value indicating a first SPO occurrence time using the booting time value;

comparing an SPO occurrence cycle to a threshold value and determining whether a second SPO is likely to occur, the SPO occurrence cycle being calculated through a difference between the first RTC value and the second RTC value; and

delaying a dummy page generation time, when the comparison result indicates that the SPO occurrence cycle is less than the threshold value.

15. The operating method of claim 14, further comprising generating the dummy page by performing a dummy program operation to program one or more pages with dummy data, when the comparison result indicates that the SPO occurrence cycle is greater than the threshold value.

16. A memory system comprising one or more storage devices including one or more processors and a program command executed by at least one of the one or more processors,

wherein the one or more storage devices and the program command control the memory system and the one or more processors to:

generate a sudden power-off (SPO) occurrence cycle using first and second real time clock (RTC) values when a first SPO occurs;

compare the SPO occurrence cycle to a threshold value;

delay a dummy page generation time by a first delay time, when the comparison result between the SPO occurrence cycle and the threshold value indicates that the SPO occurrence cycle is less than the threshold value; and

generate a dummy page, after the first delay time has elapsed, using one or more free pages or an incomplete program page, excluding valid pages, from a memory block, the incomplete program page indicating a page in which a program operation is interrupted due to an SPO.

17. The memory system of claim 16, wherein, when the comparison result between the SPO occurrence cycle and the threshold value indicates that the SPO occurrence cycle is greater than the threshold value, generating the dummy page, without delaying the dummy page generation time.