RELOCATING DATA TO LOW LATENCY MEMORY

• US 20200133585A1
• Filed: 10/30/2018
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Muchherla, Kishore Kumar, Malshe, Ashutosh, Rayaprolu, Vamsi Pavan, Ratnam, Sampath K., Singidi, Harish R., Feeley, Peter
• Granted Patent: US 11,169,747 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0649 Lifecycle management
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device

Abstract

A first data block of multiple data blocks is identified in a first portion of the memory component, the first data block being identified based on a read count associated with the first data block satisfies a first threshold criterion. A determination is made as to whether a second portion of the memory component has an amount of unused storage to store data stored at the first data block, wherein the second portion of the memory component is associated with a lower read latency than the first portion. In response to determining that the second portion of the memory component has the amount of unused storage to store the data stored at the first data block, data stored at the first data block in the first portion of the memory component is relocated to a second data block in the second portion of the memory component. An error rate is evaluated on each word line in the first data block. If there are certain word lines that have a higher error rate, and are located between other word lines having lower error rates, data corresponding to the adjacent word lines with lower error rates are relocated to a second portion of the memory component.

Claims

1. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to;

identify a first data block of a plurality of data blocks in a first portion of the memory component, the first data block being identified based on a read count associated with the first data block satisfying a first threshold criterion pertaining to the read count;

determine whether a second portion of the memory component has an amount of unused storage to store data stored at the first data block, wherein the second portion of the memory component is associated with a lower read latency than the first portion; and

in response to determining that the second portion of the memory component has the amount of unused storage to store the data stored at the first data block, relocate data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component.

2. The system of claim 1, wherein the first portion of the memory component comprises one or more quad-level cells (QLCs) and the second portion of the memory component comprises one or more single-level cell (SLCs).

3. The system of claim 1, wherein the processing device is further to:

determine whether an amount of data written to the memory component satisfies a second threshold criterion pertaining to a data threshold, wherein identifying the first data block of the plurality of data blocks in the first portion of the memory component is in response to determining that the amount of data written to the memory component satisfies the second threshold criterion.

4. The system of claim 3, wherein the processing device is further to:

determine whether a number of programming operations performed on the memory component is below an anticipated value; and

in response to determining that the number of programming operations performed on the memory component is below the anticipated value, decrease the data threshold.

5. The system of claim 1, wherein the processing device is further to:

determine whether an amount of unused memory cells of the first portion of the memory component satisfies a third threshold criterion; and

in response to determining that the amount of unused memory cells of the first portion of the memory component satisfies the third threshold condition, assign one or more of the unused memory cells of the first portion to the second portion of the memory component.

6. The system of claim 1, wherein the first threshold criterion is based on a deviation of the read count associated with the first data block with respect to a representative read count for the plurality of data blocks.

7. The system of claim 1, wherein the processing device is further to:

determine whether a number of programming operations performed on the memory component satisfies a fourth threshold condition; and

in response to determining that the number of programming operations performed on the memory component satisfies the fourth threshold condition, determine to not relocate subsequent data.

8. A method comprising:

identifying a plurality of word lines at a first portion of a memory component;

determining a corresponding error rate for each of the plurality of word lines;

determining that a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines satisfy a first threshold condition pertaining to an error rate threshold;

identifying a third word line of the plurality of word lines that is proximate to the first word line and the second word line; and

relocating, by a processing device, data stored at the third word line to a second portion of the memory component, wherein the second portion of the memory component is associated with a lower read latency than the first portion of the memory component.

9. The method of claim 8, wherein the first error rate of the first word line and the second error rate of the second word line satisfying the first threshold condition is indicative of read disturb stress associated with read operations performed on the third word line.

10. The method of claim 8, wherein the first threshold condition is based on a deviation of the first error rate and the second error rate with respect to a representative error rate for the plurality of word lines.

11. The method of claim 8, further comprising:

determining whether a number of programming operations performed on the memory component satisfies a second threshold condition; and

in response to determining that the number of programming operations performed on the memory component satisfies the second threshold condition, decreasing the error rate threshold.

12. The method of claim 8, further comprising:

determining whether a number of programming operations performed on the memory component satisfies a third threshold condition; and

in response to determining that the number of programming operations performed on the memory component satisfies the third threshold condition, determining to not relocate subsequent data.

13. The method of claim 8, wherein the first portion of the memory component comprises one or more quad-level cells (QLCs) and the second portion of the memory component comprises one or more single-level cell (SLCs).

14. The method of claim 8, wherein the memory component comprises a negative-and (NAND) type flash memory.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

identify a first data block of a plurality of data blocks in a first portion of a memory component, the first data block being identified based on a read count associated with the first data block satisfying a first threshold condition pertaining to the read count;

determine whether a second portion of the memory component has an amount of unused storage to store data stored at the first data block, wherein the second portion of the memory component is associated with a lower read latency than the first portion; and

in response to determining that the second portion of the memory component has the amount of unused storage to store the data stored at the first data block, relocate data stored at the first data block in the first portion of the memory component to a second data block in the second portion of the memory component.

16. The non-transitory computer-readable storage medium of claim 15, wherein the first portion of the memory component comprises one or more quad-level cells (QLCs) and the second portion of the memory component comprises one or more single-level cell (SLCs).

17. The non-transitory computer-readable storage medium of claim 15, wherein the processing device is further to:

determine whether an amount of data written to the memory component satisfies a second threshold condition pertaining to a data threshold, wherein identifying the first data block of the plurality of data blocks in the first portion of the memory component is in response to determining that the amount of data written to the memory component satisfies the second threshold condition.

18. The non-transitory computer-readable storage medium of claim 17, wherein the processing device is further to:

determine whether a number of programming operations performed on the memory component satisfies a third threshold condition; and

in response to determining that the number of programming operations performed on the memory component satisfying the third threshold condition, increase the data threshold.

19. The non-transitory computer-readable storage medium of claim 15, wherein the processing device is further to:

determine whether an amount of unused memory cells of the first portion of the memory component satisfies a fourth threshold condition; and

in response to determining that the amount of unused memory cells of the first portion of the memory component satisfies the fourth threshold condition, assign one or more of the unused memory cells of the first portion to the second portion of the memory component.

20. The non-transitory computer-readable storage medium of claim 15, wherein the first threshold criterion is based on a deviation of the read count associated with the first data block with respect to a representative read count for the plurality of data blocks.