SEMICONDUCTOR DEVICE FOR PERFORMING SUM-OF-PRODUCT COMPUTATION AND OPERATING METHOD THEREOF

• US 20200133635A1
• Filed: 05/09/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: LEE, Ming-Hsiu, WANG, Chao-Hung
• Granted Patent: US 10,970,044 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A semiconductor device for performing a sum-of-product computation and an operating method thereof are provided. The semiconductor device includes an inputting circuit, a scaling circuit, a computing memory and an outputting circuit. The inputting circuit is used for receiving a plurality of inputting signals. The inputting signals are voltages or currents. The scaling circuit is connected to the inputting circuit for transforming the inputting signals to be a plurality of compensated signals respectively. The compensated signals are voltages or currents. The computing memory is connected to the scaling circuit. The computing memory includes a plurality of computing cells and the compensated signals are applied to the computing cells respectively. The outputting circuit is connected to the computing memory for reading an outputting signals of the computing cells. The outputting signal is voltage or current.

Claims

1. A semiconductor device for performing a sum-of-product computation, comprising:

an inputting circuit, for receiving a plurality of inputting signals, wherein the inputting signals are voltages or currents;

a scaling circuit, connected to the inputting circuit for transforming the inputting signals to be a plurality of compensated signals respectively, wherein the compensated signals are voltages or currents;

a computing memory, connected to the scaling circuit, wherein the computing memory includes a plurality of computing cells and the compensated signals are applied to the computing cells respectively; and

an outputting circuit, connected to the computing memory for reading an outputting signal of the computing cells, wherein the outputting signal is voltage or current.

2. The semiconductor device according to claim 1, wherein the scaling circuit transforms the inputting signals according to a non-linear function.

3. The semiconductor device according to claim 2, wherein the non-linear function is an exponential function, a threshold function or a combination thereof.

4. The semiconductor device according to claim 1, wherein the scaling circuit transforms the inputting signals according to a linear function.

5. The semiconductor device according to claim 1, wherein the scaling circuit transforms the inputting signals according to a temperature of the computing memory.

6. The semiconductor device according to claim 1, wherein the scaling circuit transforms the inputting signals according to a retention time of the computing memory.

7. The semiconductor device according to claim 1, wherein each value of the compensated signals is less than each value of the inputting signals.

8. The semiconductor device according to claim 1, wherein each value of the compensated signals is larger than each value of the inputting signals.

9. The semiconductor device according to claim 1, wherein the scaling circuit is enabled according to a condition.

10. The semiconductor device according to claim 1, further comprising:

a controlling circuit for modifying at least one parameter of the scaling circuit.

11. An operating method of a semiconductor device for performing a sum-of-product computation, comprising:

receiving a plurality of inputting signals, wherein the inputting signals are voltages or currents;

transforming the inputting signals to be a plurality of compensated signals respectively, wherein the compensated signals are voltages or currents;

applying the compensated signals to a plurality of computing cells of a computing memory of the semiconductor device; and

reading an outputting signal of the computing cells, wherein the outputting signal is voltage or current.

12. The operating method of the semiconductor device according to claim 11, wherein the inputting signals are transformed according to a non-linear function.

13. The operating method of the semiconductor device according to claim 12, wherein the non-linear function is an exponential function, a threshold function or a combination thereof.

14. The operating method of the semiconductor device according to claim 11, wherein the inputting signals are transformed according to a linear function.

15. The operating method of the semiconductor device according to claim 11, wherein the inputting signals are transformed according to a temperature of the computing memory.

16. The operating method of the semiconductor device according to claim 11, wherein the inputting signals are transformed according to a retention time of the computing memory.

17. The operating method of the semiconductor device according to claim 11, wherein each of the compensated signals is less than each of the inputting signals.

18. The operating method of the semiconductor device according to claim 11, wherein each of the compensated signals is larger than each of the inputting signals.

19. The operating method of the semiconductor device according to claim 11, wherein the step of transforming the inputting signals is performed if a condition is satisfied.

20. The operating method of the semiconductor device according to claim 11, further comprising:

modifying at least one parameter of the step of transforming the inputting signals.