GENERATING CODE FOR FUNCTION CALLS THAT USE MULTIPLE ADDRESSING MODES

• US 20200133648A1
• Filed: 10/31/2018
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schmidt, William J., Weigand, Ulrich, Modra, Alan David
• Granted Patent: US 10,671,363 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 8/434 Pointers; Aliasing
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space
• CPC Class Codes: G06F 8/443 Optimisation

Abstract

A compiler and linker include multiple addressing mode resolvers that generate code to resolve a plurality of function calls that use different addressing modes. A first addressing mode is defined where a first address for first data is specified as an offset from a base pointer. A second, relative addressing mode is defined where a second address for second data is specified as an offset from an address of an instruction that references the second data. The generated code assures correct operation when functions with different addressing modes are included in the computer program. The generated code preserves a base pointer when executing a function that uses relative addressing, when needed. The compiler inserts one or more relocation markers that trigger certain functions in the linker. A linker resolves the relocation markers inserted by the compiler, and generates code, when needed, that handles a mismatch between addressing modes.

Claims

1. An apparatus comprising:

at least one processor;

a memory coupled to the at least one processor; and

a linker residing in the memory and executed by the at least one processor, the linker comprising;

a multiple addressing mode resolver that generates code to resolve a plurality of function calls in a computer program, wherein at least one of the plurality of function calls has a caller instruction that references a callee function, wherein the plurality of function calls includes a first function call that comprises code that uses a first addressing mode where a first address for first data is specified as an offset from a base pointer, where the base pointer is stored in a fixed processor register, wherein the plurality of function calls includes a second function call that comprises code that uses a relative addressing mode where a second address for second data is specified as an offset from an address of an instruction that references the second data, wherein the relative addressing mode does not preserve the base pointer stored in the fixed processor register.

2. The apparatus of claim 1 wherein the multiple addressing mode resolver scans a text portion of the computer program to locate a relocation marker inserted by a compiler to indicate the caller instruction at the relocation marker does not need the base pointer.

3. The apparatus of claim 2 wherein the multiple addressing mode resolver determines when a target of the caller instruction at the relocation marker can be resolved from the text portion.

4. The apparatus of claim 3 wherein, when the target of the caller instruction cannot be resolved from the text portion, the multiple addressing mode resolver generates stub code to resolve the target of the caller instruction at run-time.

5. The apparatus of claim 4 wherein the multiple address mode resolver modifies the caller instruction to target the stub code.

6. The apparatus of claim 3 wherein, when a target of the caller instruction can be resolved from the text portion, the multiple addressing mode resolver determines whether the callee function of the caller instruction requires the base pointer.

7. The apparatus of claim 6 wherein, when the callee function of the caller instruction does not require the base pointer, the multiple addressing mode resolver modifies the caller instruction to target the callee function.

8. The apparatus of claim 6 wherein, when the callee function of the caller instruction requires the base pointer, the multiple addressing mode resolver generates stub code to directly resolve a target of the caller instruction, and optimized so there is no save of the first fixed processor register in the stub code.

9. The apparatus of claim 8 wherein the multiple address mode resolver modifies the caller instruction to target the stub code.

10. An apparatus comprising:

at least one processor;

a memory coupled to the at least one processor; and

a linker residing in the memory and executed by the at least one processor, the linker comprising;

a multiple addressing mode resolver that generates code to resolve a plurality of function calls in a computer program, wherein at least one of the plurality of function calls has a caller instruction that references a callee function, wherein the plurality of function calls includes a first function call that comprises code that uses a first addressing mode where a first address for first data is specified as an offset from a base pointer, where the base pointer is stored in a fixed processor register, wherein the plurality of function calls includes a second function call that comprises code that uses a relative addressing mode where a second address for second data is specified as an offset from an address of an instruction that references the second data, wherein the relative addressing mode does not preserve the base pointer stored in the fixed processor register, wherein the multiple addressing mode resolver scans a text portion of the computer program to locate a relocation marker inserted by a compiler to indicate the caller instruction at the relocation marker does not need the base pointer and determines when a target of the caller instruction at the relocation marker can be resolved from the text portion, and when the target of the caller instruction cannot be resolved from the text portion, the multiple addressing mode resolver generates first stub code to resolve the target of the caller instruction at run-time and modifies the caller instruction to target the first stub code, and when a target of the caller instruction can be resolved from the text portion, the multiple addressing mode resolver determines whether the callee function of the caller instruction requires the base pointer, and when the callee function of the caller instruction does not require the base pointer, the multiple addressing mode resolver modifies the caller instruction to target the callee function, and when the callee function of the caller instruction requires the base pointer, the multiple addressing mode resolver generates second stub code to directly resolve a target of the caller instruction, and optimized so there is no save of the first fixed processor register in the second stub code, and modifies the caller instruction to target the second stub code.

11. A method for linking a computer program, the method comprising:

scanning a text portion of a computer program for a plurality of function calls; and

generating code to resolve the plurality of function calls, wherein at least one of the plurality of function calls has a caller instruction that references a callee function, wherein the plurality of function calls includes a first function call that comprises code that uses a first addressing mode where a first address for first data is specified as an offset from a base pointer, where the base pointer is stored in a fixed processor register, wherein the plurality of function calls includes a second function call that comprises code that uses a relative addressing mode where a second address for second data is specified as an offset from an address of an instruction that references the second data, wherein the relative addressing mode does not preserve the base pointer stored in the fixed processor register.

12. The method of claim 11 further comprising scanning the text portion of the computer program to locate a relocation marker inserted by a compiler to indicate the caller instruction at the relocation marker does not need the base pointer.

13. The method of claim 11 further comprising determining when a target of the caller instruction at the relocation marker can be resolved from the text portion.

14. The method of claim 13 further comprising, when the target of the caller instruction cannot be resolved from the text portion, generating stub code to resolve the target of the caller instruction at run-time.

15. The method of claim 14 further comprising modifying the caller instruction to target the stub code.

16. The method of claim 13 further comprising, when a target of the caller instruction can be resolved from the text portion, determining whether the callee function of the caller instruction requires the base pointer.

17. The method of claim 16 further comprising, when the callee function of the caller instruction does not require the base pointer, modifying the caller instruction to target the callee function.

18. The method of claim 16 further comprising, when the callee function of the caller instruction requires the base pointer, generating stub code to directly resolve a target of the caller instruction, and optimized so there is no save of the first fixed processor register in the stub code.

19. The method of claim 18 further comprising modifying the caller instruction to target the stub code.