TECHNIQUES FOR DYNAMIC PROXIMITY BASED ON-DIE TERMINATION

• US 20200133669A1
• Filed: 12/23/2019
• Published: 04/30/2020
• Est. Priority Date: 12/23/2019
• Status: Active Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: QAWAMI, Shekoufeh, SUNDARAM, Rajesh, HIEMSTRA, Sheldon G., SHAH, Setul M., MORNING-SMITH, Andrew, JAYACHANDRAN, Sowmiya
• Application Number:
  US16/725,521
• Publication Number:
  US 20200133669A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/225 Clock input buffers
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

Techniques for proximity based on-die termination (ODT) include a memory device determining what ODT setting to apply during execution of a command by another memory device that is coupled to a same data channel as the memory device based on the memory device'"'"'s proximity to the other memory device and whether the command is a read command or a write command.

Claims

1. A memory device comprising:

one or more registers arranged to maintain on-die termination (ODT) settings; and

control circuitry to;

receive an indication that a command is to be executed by a separate memory device coupled with a same data channel;

read the one or more registers to determine what ODT setting to apply during execution of the command based on a first group identifier that indicates the separate memory device'"'"'s proximity to the memory device and based on whether the command is a read command or a write command.

2. The memory device of claim 1, comprising the memory device located on a first package that includes the separate memory device, the memory device arranged to be a terminating memory device for the first package.

3. The memory device of claim 2, comprising the first group identifier assigned to the first package to indicate that the separate memory device is located on a same package, the command is a write command, the control circuitry to cause the memory device to provide a Hi_z ODT setting during a write operation to the separate memory device.

4. The memory device of claim 1, comprising the memory device located on a first package that includes at least one other memory device, the memory device arranged to be a terminating memory device for the first package, the separate memory device located on a second package, the first group identifier assigned to the second package, the first group identifier to indicate that the separate memory device is located on a different package.

5. The memory device of claim 4, comprising the command is a read command, the control circuitry to cause the memory device to provide a first ODT setting during a read operation if the second package is located adjacent to or near to the first package or provide a second ODT setting during the read operation if the second package is not located adjacent to the first package.

6. The memory device of claim 1, comprising the command is received from a controller of a storage device.

7. The memory device of claim 6, comprising the memory device including non-volatile types of memory, the storage device is a solid state drive.

8. The memory device of claim 7, the non-volatile types of memory comprising a phase change memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an anti-ferroelectric memory, a resistive memory including a metal oxide base, an oxygen vacancy base and a conductive bridge random access memory (CB-RAM), a spintronic magnetic junction memory, a magnetic tunneling junction (MTJ) memory, a domain wall (DW) and spin orbit transfer (SOT) memory, a thyristor based memory array, a magnetoresistive random access memory (MRAM) that incorporates memristor technology or a spin transfer torque MRAM (STT-MRAM).

9. An apparatus comprising:

input/output (I/O) interface circuitry to couple with a first memory device; and

circuitry to execute program logic, the program logic to;

program a first register at the first memory device via the I/O interface circuitry to cause the first register to indicate multiple on-die termination (ODT) types to select when the first memory device is a terminating memory device for a first group of memory devices, the multiple ODT types based on whether a read command or a write command is to be executed by a second memory device included in the first group of memory device or is to be executed by a third memory device included in a second group of memory devices; and

program a second register at the first memory device via the I/O interface circuitry to cause the second register to indicate at least two ODT types having separate ODT settings to apply based on whether a write command is to be executed by the second memory device or the third memory device.

10. The apparatus of claim 9, comprising the first group of memory devices located on a first package assigned a first group identifier, the second group of memory devices located on a second package assigned to a second group identifier, wherein a fourth memory device included in a third group of memory devices is located on a third package assigned a third group identifier, the first and the second and the third packages coupled to the I/O interface circuitry via a same data bus, the second package located adjacent or near to the first package, the third package not located adjacent to the first package.

11. The apparatus of claim 10, further comprising the program logic to:

program a third register at the first memory device to indicate a first ODT setting and a second ODT setting to selectively apply when the first memory device is the terminating memory device for the first group of memory devices and the command is a read command, wherein the first memory device is to apply the first ODT setting if the read command is to the third memory device or is to apply the second ODT setting if the read command is to the fourth memory device.

12. The apparatus of claim 9, comprises the first, the second and the third memory devices including non-volatile types of memory, the apparatus is a controller for a solid state drive that includes the first, the second and the third memory devices.

13. The apparatus of claim 12, the non-volatile types of memory comprising a phase change memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an anti-ferroelectric memory, a resistive memory including a metal oxide base, an oxygen vacancy base and a conductive bridge random access memory (CB-RAM), a spintronic magnetic junction memory, a magnetic tunneling junction (MTJ) memory, a domain wall (DW) and spin orbit transfer (SOT) memory, a thyristor based memory array, a magnetoresistive random access memory (MRAM) that incorporates memristor technology or a spin transfer torque MRAM (STT-MRAM).

14. A storage device comprising:

a controller having input/output (I/O) interface circuitry to couple with multiple groups of memory devices via a same data channel; and

a memory device of a first group of the multiple groups of memory devices, the memory device to include;

one or more registers arranged to maintain on-die termination (ODT) settings; and

control circuitry to;

receive an indication that a command from the controller is to be executed by a separate memory device coupled with the same data channel;

read the one or more registers to determine what ODT setting to apply during execution of the command based on a first group identifier that indicates the separate memory device'"'"'s proximity to the memory device and based on whether the command is a read command or a write command.

15. The storage device of claim 14, comprising the first group of the multiple groups of memory devices is located on a first package, the first group also includes the separate memory device, the memory device arranged to be a terminating memory device for the first group.

16. The storage device of claim 15, comprising the first group identifier assigned to the first group to indicate that the separate memory device is located on a same package, the command is a write command, the control circuitry to cause the memory device to provide a Hi_z ODT setting during a write operation to the separate memory device.

17. The storage device of claim 14, comprising the first group of the multiple groups of memory devices is located on a first package, the first group also includes the separate memory device, the memory device arranged to be a terminating memory device for the first group, the separate memory device included in a second group of the multiple groups of memory devices that are located on a second package, the first group identifier assigned to the second group, the first group identifier to indicate that the separate memory device is located on a different package.

18. The storage device of claim 17, comprising the command is a read command, the control circuitry to cause the memory device to provide a first ODT setting during a read operation if the second package is located adjacent to or near to the first package or provide a second ODT setting during the read operation if the second package is not located adjacent to the first package.

19. The storage device of claim 14, comprising the memory device including non-volatile types of memory, the storage device is a solid state drive.

20. The storage device of claim 19, the non-volatile types of memory comprising a phase change memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an anti-ferroelectric memory, a resistive memory including a metal oxide base, an oxygen vacancy base and a conductive bridge random access memory (CB-RAM), a spintronic magnetic junction memory, a magnetic tunneling junction (MTJ) memory, a domain wall (DW) and spin orbit transfer (SOT) memory, a thyristor based memory array, a magnetoresistive random access memory (MRAM) that incorporates memristor technology or a spin transfer torque MRAM (STT-MRAM).