CIRCUITRY AND METHOD

• US 20200133673A1
• Filed: 10/16/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: BOUZGUARROU, Houdhaifa, BOLBENES, Guillaume, CONSALES, Vincenzo
• Granted Patent: US 11,281,467 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables

Abstract

Circuitry comprises a prediction register having one or more entries each storing prediction data; prediction circuitry configured to map a value of the stored prediction data to a prediction of whether or not a branch represented by a given branch instruction is predicted to be taken, according to a data mapping; and control circuitry configured to selectively vary the data mapping between the prediction and the value of the stored prediction data.

Claims

1. Circuitry comprising:

a prediction register having one or more entries each storing prediction data;

prediction circuitry configured to map a value of the stored prediction data to a prediction of whether or not a branch represented by a given branch instruction is predicted to be taken, according to a data mapping; and

control circuitry configured to selectively vary the data mapping between the prediction and the value of the stored prediction data.

2. Circuitry according to claim 1, in which the control circuitry is responsive to a trigger event to vary the data mapping between the prediction and the value of the stored prediction data.

3. Circuitry according to claim 2, in which the trigger event comprises an event selected from the list consisting of:

receipt of an interrupt by a processing element associated with the circuitry;

a change of state of a hardware control signal;

a change of a data value stored in a predetermined register or storage location; and

execution of a predetermined program instruction by the processing element associated with the circuitry.

4. Circuitry according to claim 1, in which:

the prediction circuitry is configured to apply the data mapping in dependence upon a key value; and

the control circuitry is configured to change the key value.

5. Circuitry according to claim 4, comprising a processing element;

in which the control circuitry is configured to use a key value dependent upon at least a current processing context of the processing element.

6. Circuitry according to claim 5, in which the control circuitry is configured to use a key value dependent upon at least a memory page of program code containing the given branch instruction.

7. Circuitry according to claim 6, comprising a region table to store a plurality of entries, each entry defining an association between at least a memory page, a memory page identifier, a processor context identifier and the key value.

8. Circuitry according to claim 7, in which the control circuitry is configured to generate a key value for use with a given memory page in a given processor context in response to initiation of allocation of an entry in the region table to the given memory page in the given processor context.

9. Circuitry according to claim 4, in which the data mapping comprises an encryption function defined at least in part by the key value.

10. Circuitry according to claim 1, in which the prediction circuitry is configured to modify the stored prediction data in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not.

11. Circuitry according to claim 10, in which:

the prediction register comprises two or more entries storing respective prediction data;

the prediction circuitry is configured to select a respective prediction register entry for the given branch instruction.

12. Circuitry according to claim 11, in which each prediction register comprises a plurality of prediction data values, and the prediction circuitry is configured to select one of the prediction data values for use as the prediction data for the given branch instruction according to a permutation of most recent resolutions of whether the branch represented by the given branch instruction is taken or not.

13. Circuitry comprising:

means for storing one or more entries each storing prediction data;

means for mapping a value of the stored prediction data to a prediction of whether or not a branch represented by a given branch instruction is predicted to be taken, according to a data mapping; and

means for selectively varying the data mapping between the prediction and the value of the stored prediction data.

14. A method comprising:

storing one or more entries each representing prediction data;

mapping a value of the stored prediction data to a prediction of whether or not a branch represented by a given branch instruction is predicted to be taken, according to a data mapping; and

selectively varying the data mapping between the prediction and the value of the stored prediction data.