CIRCUITRY AND METHOD

• US 20200133674A1
• Filed: 10/18/2019
• Published: 04/30/2020
• Est. Priority Date: 10/30/2018
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: BOUZGUARROU, Houdhaifa, CONSALES, Vincenzo
• Granted Patent: US 11,226,824 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 21/75 by inhibiting the analysis of circuitry or operation
• CPC Class Codes: G06F 2207/7219 Countermeasures against side channel or fault attacks
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables

Abstract

Circuitry comprises a prediction register storing a plurality of entries each having respective data values for association with one or more branch instructions; prediction circuitry to detect, using prediction data derived by a mapping function from the stored data values associated with a given branch instruction, whether or not a branch represented by the given branch instruction is predicted to be taken; update circuitry to modify the stored data values associated with the given branch instruction in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not; and control circuitry configured to selectively alter one or more of the data values other than data values associated with the given branch instruction.

Claims

1. Circuitry comprising:

a prediction register storing a plurality of entries each having respective data values for association with one or more branch instructions;

prediction circuitry to detect, using prediction data derived by a mapping function from the stored data values associated with a given branch instruction, whether or not a branch represented by the given branch instruction is predicted to be taken;

update circuitry to modify the stored data values associated with the given branch instruction in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not; and

control circuitry configured to selectively alter one or more of the data values other than data values associated with the given branch instruction.

2. The circuitry of claim 1, in which the control circuitry is configured to modify the stored data values of a set of one or more prediction register entries other than an entry associated with the given branch instruction.

3. The circuitry of claim 2, in which the set of one or more prediction register entries comprises a predetermined set of prediction register entries.

4. The circuitry of claim 2, in which the set of one or more prediction register entries comprises a random or pseudorandom set of prediction register entries.

5. The circuitry of claim 2, in which, in response to the update circuitry modifying the stored data values associated with the given branch instruction according to a first modification in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not, the control circuitry is configured to apply a second modification different to the first modification to at least one of the set of prediction register entries.

6. The circuitry of claim 5, in which:

the first modification is selected from candidate modifications of opposite polarities, each dependent upon whether the given branch instruction is resolved as a taken branch instruction or an untaken branch instruction; and

the second modification has the opposite polarity to the first modification.

7. The circuitry of claim 2, in which the control circuitry is configured to operate in response to an indicator associated with the given branch instruction.

8. The circuitry of claim 1, in which:

the prediction register comprises two or more entries;

the prediction circuitry is configured to select a respective prediction register entry for the given branch instruction.

9. The circuitry of claim 8, in which each prediction register comprises a plurality of prediction data values, and the prediction circuitry is configured to select one of the prediction data values for use as the prediction data for the given branch instruction according to a permutation of most recent resolutions of whether the branch represented by the given branch instruction is taken or not.

10. Circuitry comprising:

a prediction register having a plurality of entries each storing prediction data;

mapping circuitry to map branch instructions to respective entries of the prediction register;

detection circuitry to detect, from the stored prediction data of the prediction register entry mapped to a given branch instruction, whether or not a branch represented by the given branch instruction is predicted to be taken; and

update circuitry to modify the stored prediction data of the prediction register entry mapped to a given branch instruction in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not, the update circuitry comprising control circuitry to inhibit updating of one or more selected prediction register entries in response to control data specifying the one or more selected prediction register entries.

11. A method comprising:

storing a plurality of entries each having respective data values for association with one or more branch instructions;

detecting, using prediction data derived by a mapping function from the stored data values associated with a given branch instruction, whether or not a branch represented by the given branch instruction is predicted to be taken;

modifying the stored data values associated with the given branch instruction in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not; and

selectively altering one or more of the data values other than data values associated with the given branch instruction.

12. A method comprising:

storing a plurality of entries each providing prediction data;

mapping branch instructions to respective entries of the prediction register;

detecting, from the stored prediction data of the prediction register entry mapped to a given branch instruction, whether or not a branch represented by the given branch instruction is predicted to be taken;

updating the stored prediction data of the prediction register entry mapped to a given branch instruction in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not; and

inhibiting the updating step from updating one or more selected prediction register entries in response to control data specifying the one or more selected prediction register entries.