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APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION

  • US 20200133679A1
  • Filed: 10/31/2018
  • Published: 04/30/2020
  • Est. Priority Date: 10/31/2018
  • Status: Active Grant
First Claim
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1. A processor core comprising:

  • at least one logical core;

    a branch predictor to predict a target instruction of an indirect branch instruction;

    an instruction execution pipeline to perform at least one data fetch operation for the target instruction before execution of the target instruction; and

    a model specific register to store an indirect branch restricted speculation bit for a first logical core of the at least one logical core that, when set after a transition of the first logical core to a more privileged predictor mode, prevents the branch predictor from predicting the target instruction of the indirect branch instruction for the first logical core based on software executed in a less privileged predictor mode by any of the at least one logical core.

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