APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION
First Claim
1. A processor core comprising:
- at least one logical core;
a branch predictor to predict a target instruction of an indirect branch instruction;
an instruction execution pipeline to perform at least one data fetch operation for the target instruction before execution of the target instruction; and
a model specific register to store an indirect branch restricted speculation bit for a first logical core of the at least one logical core that, when set after a transition of the first logical core to a more privileged predictor mode, prevents the branch predictor from predicting the target instruction of the indirect branch instruction for the first logical core based on software executed in a less privileged predictor mode by any of the at least one logical core.
1 Assignment
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Accused Products
Abstract
Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
33 Citations
24 Claims
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1. A processor core comprising:
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at least one logical core; a branch predictor to predict a target instruction of an indirect branch instruction; an instruction execution pipeline to perform at least one data fetch operation for the target instruction before execution of the target instruction; and a model specific register to store an indirect branch restricted speculation bit for a first logical core of the at least one logical core that, when set after a transition of the first logical core to a more privileged predictor mode, prevents the branch predictor from predicting the target instruction of the indirect branch instruction for the first logical core based on software executed in a less privileged predictor mode by any of the at least one logical core. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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transitioning a first logical core of at least one logical core of a processor core of a processor to a more privileged predictor mode from a less privileged predictor mode; setting an indirect branch restricted speculation bit for the first logical core in a model specific register of the processor after the transitioning of the first logical core to the more privileged predictor mode to prevent a branch predictor of the processor from predicting a target instruction of an indirect branch instruction for the first logical core based on software executed in the less privileged predictor mode by any of the at least one logical core; and performing at least one data fetch operation with an instruction execution pipeline of the processor core for the target instruction before execution of the target instruction by the first logical core. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
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transitioning a first logical core of at least one logical core of a processor core of a processor to a more privileged predictor mode from a less privileged predictor mode; setting an indirect branch restricted speculation bit for the first logical core in a model specific register of the processor after the transitioning of the first logical core to the more privileged predictor mode to prevent a branch predictor of the processor from predicting a target instruction of an indirect branch instruction for the first logical core based on software executed in the less privileged predictor mode by any of the at least one logical core; and performing at least one data fetch operation with an instruction execution pipeline of the processor core for the target instruction before execution of the target instruction by the first logical core. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification