MANAGING PIPELINE INSTRUCTION INSERTION FOR RECEIVED EXTERNAL INSTRUCTIONS
First Claim
1. An integrated circuit comprising:
- at least a first processor core executing instructions in a pipeline configured for out-of-order issuing of instructions;
translation circuitry configured to handle translation of virtual addresses to physical addresses, the handling including;
storing translations between virtual addresses and physical addresses in a translation lookaside buffer, andupdating at least one translation lookaside buffer entry in the translation lookaside buffer based at least in part on an external instruction received from outside the first processor core; and
instruction management circuitry configured to manage external instructions received from outside the first processor core, the managing including;
updating issue status information for each of a plurality of instructions stored in an instruction queue,processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, the identified instructions including a first queued instruction and a second queued instruction, andinserting an instruction for performing an operation associated with the first external instruction into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
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Accused Products
Abstract
In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.
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Citations
16 Claims
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1. An integrated circuit comprising:
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at least a first processor core executing instructions in a pipeline configured for out-of-order issuing of instructions; translation circuitry configured to handle translation of virtual addresses to physical addresses, the handling including; storing translations between virtual addresses and physical addresses in a translation lookaside buffer, and updating at least one translation lookaside buffer entry in the translation lookaside buffer based at least in part on an external instruction received from outside the first processor core; and instruction management circuitry configured to manage external instructions received from outside the first processor core, the managing including; updating issue status information for each of a plurality of instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, the identified instructions including a first queued instruction and a second queued instruction, and inserting an instruction for performing an operation associated with the first external instruction into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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executing instructions in a pipeline of a first processor core, the pipeline being configured for out-of-order issuing of instructions; handling translation of virtual addresses to physical addresses, the handling including storing translations between virtual addresses and physical addresses in a translation lookaside buffer, and updating at least one translation lookaside buffer entry in the translation lookaside buffer based at least in part on an external instruction received from outside the first processor core; and managing external instructions received from outside the first processor core, the managing including; updating issue status information for each of a plurality of instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, the identified instructions including a first queued instruction and a second queued instruction, and inserting an instruction for performing an operation associated with the first external instruction into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification