MANAGING PIPELINE INSTRUCTION INSERTION FOR RECEIVED EXTERNAL INSTRUCTIONS

• US 20200133680A1
• Filed: 10/26/2018
• Published: 04/30/2020
• Est. Priority Date: 10/26/2018
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Mukherjee, Shubhendu Sekhar, Carlson, David Albert, Bertone, Michael
• Granted Patent: US 10,817,300 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/683 Invalidation
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3854 Instruction completion, e.g. retiring, committing or graduating

Abstract

In a pipeline configured for out-of-order issuing, handling translation of virtual addresses to physical addresses includes: storing translations in a translation lookaside buffer (TLB), and updating at least one entry in the TLB based at least in part on an external instruction received from outside a first processor core. Managing external instructions includes: updating issue status information for each of multiple instructions stored in an instruction queue, processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, including a first queued instruction and a second queued instruction. An instruction for performing an operation associated with the first external instruction is inserted into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.

Claims

1. An integrated circuit comprising:

at least a first processor core executing instructions in a pipeline configured for out-of-order issuing of instructions;

translation circuitry configured to handle translation of virtual addresses to physical addresses, the handling including;

storing translations between virtual addresses and physical addresses in a translation lookaside buffer, and

updating at least one translation lookaside buffer entry in the translation lookaside buffer based at least in part on an external instruction received from outside the first processor core; and

instruction management circuitry configured to manage external instructions received from outside the first processor core, the managing including;

updating issue status information for each of a plurality of instructions stored in an instruction queue,

processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, the identified instructions including a first queued instruction and a second queued instruction, and

inserting an instruction for performing an operation associated with the first external instruction into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.

2. The integrated circuit of claim 1, wherein updating at least one translation lookaside buffer entry in the translation lookaside buffer based at least in part on an external instruction received from outside the first processor core into the pipeline comprises invalidating at least one translation lookaside buffer entry in the translation lookaside buffer before an associated synchronization operation is committed by the commit stage.

3. The integrated circuit of claim 2, wherein the managing further includes maintaining an indication of the program order for the plurality of instructions as they are stored in the instruction queue.

4. The integrated circuit of claim 3, wherein the first queued instruction is an unissued instruction that is adjacent to an issued instruction in the program order, with no later instructions in the program order having been issued, and the second queued instruction is an unissued instruction that is adjacent to an issued instruction in the program order, with all earlier instructions in the program order having been issued.

5. The integrated circuit of claim 4, wherein processing the issue status information includes scanning the instruction queue from the latest in the program order to the earliest in the program order, identifying the first queued instruction and second queued instruction according to their respective issue status information.

6. The integrated circuit of claim 2, wherein the operation associated with the first external instruction comprises the associated synchronization operation.

7. The integrated circuit of claim 1, wherein the plurality of instructions include at least two instructions that are issued out-of-order relative to each other, according to a program order for the plurality of instructions, in at least one issue stage of the pipeline, and the plurality of instructions are committed in-order, according to the program order, in at least one commit stage of the pipeline.

8. The integrated circuit of claim 1, wherein at least one second processor core in the integrated circuit provides the first external instruction.

9. A method comprising:

executing instructions in a pipeline of a first processor core, the pipeline being configured for out-of-order issuing of instructions;

handling translation of virtual addresses to physical addresses, the handling including

storing translations between virtual addresses and physical addresses in a translation lookaside buffer, and

updating at least one translation lookaside buffer entry in the translation lookaside buffer based at least in part on an external instruction received from outside the first processor core; and

managing external instructions received from outside the first processor core, the managing including;

updating issue status information for each of a plurality of instructions stored in an instruction queue,

processing the issue status information in response to receiving a first external instruction to identify at least two instructions in the instruction queue, the identified instructions including a first queued instruction and a second queued instruction, and

inserting an instruction for performing an operation associated with the first external instruction into a stage of the pipeline so that the operation associated with the first external instruction is committed before the first queued instruction is committed and after the second queued instruction is committed.

10. The method of claim 9, wherein updating at least one translation lookaside buffer entry in the translation lookaside buffer based at least in part on an external instruction received from outside the first processor core into the pipeline comprises invalidating at least one translation lookaside buffer entry in the translation lookaside buffer before an associated synchronization operation is committed by the commit stage.

11. The method of claim 10, wherein the managing further includes maintaining an indication of the program order for the plurality of instructions as they are stored in the instruction queue.

12. The method of claim 11, wherein the first queued instruction is an unissued instruction that is adjacent to an issued instruction in the program order, with no later instructions in the program order having been issued, and the second queued instruction is an unissued instruction that is adjacent to an issued instruction in the program order, with all earlier instructions in the program order having been issued.

13. The method of claim 12, wherein processing the issue status information includes scanning the instruction queue from the latest in the program order to the earliest in the program order, identifying the first queued instruction and second queued instruction according to their respective issue status information.

14. The method of claim 10, wherein the operation associated with the first external instruction comprises the associated synchronization operation.

15. The method of claim 9, wherein the plurality of instructions include at least two instructions that are issued out-of-order relative to each other, according to a program order for the plurality of instructions, in at least one issue stage of the pipeline, and the plurality of instructions are committed in-order, according to the program order, in at least one commit stage of the pipeline.

16. The method of claim 9, wherein at least one second processor core in an integrated circuit that includes the first processor core provides the first external instruction.