AN APPARATUS AND METHOD FOR MANAGING USE OF CAPABILITIES

• US 20200133710A1
• Filed: 04/19/2018
• Published: 04/30/2020
• Est. Priority Date: 05/05/2017
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: BARNES, Graeme Peter
• Granted Patent: US 11,461,128 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2209/481 Exception handling
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/35 Indirect addressing
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/468 Specific access rights for resources, e.g. using capability register
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An apparatus and method are provided for managing use of capabilities. The apparatus has processing circuitry to execute instructions, and a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain operations performed by the processing circuitry when executing instructions. The processing circuitry is operable at a plurality of exception levels, each exception level having different software execution privilege. Further, capability configuration storage is provided to identify capability configuration information for each of the plurality of exception levels. For each exception level, the capability configuration information identifies at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by capabilities. During a switch operation from a source exception level to a target exception level, the capability configuration information in the capability configuration storage pertaining to at least one of the source exception level and the destination exception level is used to determine how execution state of the processing circuitry is managed during the switch operation. This provides a great deal of flexibility in the management of capabilities.

Claims

1. An apparatus comprising:

processing circuitry to execute instructions, the processing circuitry being operable at a plurality of exception levels, each exception level having different software execution privilege;

a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain operations performed by the processing circuitry when executing said instructions; and

capability configuration storage to identify capability configuration information for each of said plurality of exception levels, for each exception level the capability configuration information identifying at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by said capabilities; and

during a switch operation from a source exception level to a target exception level, the capability configuration information in the capability configuration storage pertaining to at least one of the source exception level and the destination exception level is used to determine how execution state of the processing circuitry is managed during the switch operation.

2. An apparatus as claimed in claim 1, wherein the processing circuitry is arranged to use an exception mechanism to transition between said plurality of exception levels, and when exception entry causes the switch operation from the source exception level to the destination exception level, the processing circuitry is arranged to determine return address information to be preserved for the source exception level with reference to the capability configuration information pertaining to the source exception level.

3. An apparatus as claimed in claim 2, wherein:

when the capability configuration information pertaining to the source exception level identifies that the operations performed by the processing circuitry when executing instructions at said source exception level are constrained by said capabilities, the processing circuitry is arranged to determine said return address information with reference to a program counter capability, and to store the return address information as a capability within one of said capability storage elements designated as a return address capability storage element; and

otherwise, the processing circuitry is arranged to determine said return address information with reference to a program counter value, and to store the return address information as a return address value within a return address storage element.

4. An apparatus as claimed in claim 3, wherein the return address storage element is formed by a field within the return address capability storage element.

5. An apparatus as claimed in claim 4, wherein when the return address information is stored as the return address value within the return address storage element, at least one remaining field of the return address capability storage element is set to a first default value.

6. An apparatus as claimed in claim 5, wherein all remaining fields are set to the first default value by zero extending the return address value.

7. An apparatus as claimed in claim 1, wherein the processing circuitry is arranged to use an exception mechanism to transition between said plurality of exception levels, and when exception entry causes the switch operation from the source exception level to the destination exception level, the processing circuitry is arranged to determine an initial execution state of the processing circuitry for the destination exception level with reference to the capability configuration information pertaining to the destination exception level.

8. An apparatus as claimed in claim 7, wherein:

when the capability configuration information pertaining to the destination exception level identifies that the operations performed by the processing circuitry when executing instructions at said destination exception level are constrained by said capabilities, the processing circuitry is arranged to generate an initial program counter capability for the destination exception level using exception entry address capability information stored in a capability control storage element; and

otherwise, the processing circuitry is arranged to generate an initial program counter value using exception entry address information stored in a control storage element.

9. An apparatus as claimed in claim 8, wherein said control storage element is formed by a field within said capability control storage element.

10. An apparatus as claimed in claim 8, further comprising:

a program counter capability storage element to store the initial program counter capability;

the processing circuitry being arranged, when generating the initial program counter value instead of the initial program counter capability, to store the initial program counter value within a first field of the program counter capability storage element.

11. An apparatus as claimed in claim 10, wherein when the processing circuitry stores the initial program counter value within the first field of the program counter capability storage element, remaining fields of the program counter capability storage element are arranged to be set to a second default value.

12. An apparatus as claimed in claim 11, wherein said second default value causes the program counter capability storage element to represent a maximum capability for the processing circuitry, to ensure that the processing circuitry'"'"'s use of the initial program counter value is unconstrained by the content of the program counter capability storage element.

13. An apparatus as claimed in claim 1, wherein the processing circuitry is arranged to use an exception mechanism to transition between said plurality of exception levels, and when exception exit causes the switch operation from the source exception level to the destination exception level, the processing circuitry is arranged to determine a return execution state of the processing circuitry for the destination exception level with reference to the capability configuration information pertaining to the destination exception level.

14. An apparatus as claimed in claim 13, wherein:

when the capability configuration information pertaining to the destination exception level identifies that the operations performed by the processing circuitry when executing instructions at said destination exception level are constrained by said capabilities, the processing circuitry is arranged to generate a return program counter capability for the destination exception level using return address information stored as a capability within one of said capability storage elements designated as a return address capability storage element; and

otherwise, the processing circuitry is arranged to generate a return program counter value using return address information stored as a return address value within a return address storage element.

15. An apparatus as claimed in claim 14, further comprising:

a program counter capability storage element to store the return program counter capability;

the processing circuitry being arranged when generating the return program counter value instead of the return program counter capability, to store the return program counter value within a first field of the program counter capability storage element.

16. An apparatus as claimed in claim 15, wherein when the processing circuitry stores the return program counter value within the first field of the program counter capability storage element, remaining fields of the program counter capability storage element are arranged to be set to a third default value.

17. An apparatus as claimed in claim 16, wherein said third default value causes the program counter capability storage element to represent a maximum capability for the processing circuitry, to ensure that the processing circuitry'"'"'s use of the return program counter value is unconstrained by the content of the program counter capability storage element.

18. An apparatus as claimed in claim 1, wherein:

said plurality of exception levels are arranged as a hierarchy of exception levels, such that software executing at a higher exception level in said hierarchy has ability to constrain at least some behaviour of software executing at a lower exception level in said hierarchy; and

for each exception level the capability configuration information is arranged to further identify whether software executing at that exception level is able to manage capabilities used to constrain the operations performed by the processing circuitry when executing instructions at at least one of the same exception level and a lower exception level.

19. An apparatus as claimed in claim 18, wherein:

when the capability configuration information for a particular exception level identifies that that particular exception level is unable to manage capabilities, then at least when the particular exception level is an exception level other than a lowest exception level the capability configuration information for said particular exception level will further identify that the operations performed by the processing circuitry when executing instructions at said particular exception level are unconstrained by said capabilities.

20. An apparatus as claimed in claim 19, wherein:

when the capability configuration information for said particular exception level identifies that that particular exception level is unable to manage capabilities, the capability configuration information for each lower exception level than said particular exception level will identify that that lower exception level cannot manage capabilities and, at least when that lower exception level is an exception level other than a lowest exception level, will further identify that the operations performed by the processing circuitry when executing instructions at said lower exception level are unconstrained by said capabilities.

23. A virtual machine computer program comprising program instructions to control a host data processing apparatus to provide an instruction execution environment corresponding to the apparatus according to claim 1.

24. A computer-readable storage medium storing the virtual machine computer program according to claim 23.

21. A method of managing use of capabilities within an apparatus having processing circuitry to execute instructions, the processing circuitry being operable at a plurality of exception levels, each exception level having different software execution privilege, and a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain operations performed by the processing circuitry when executing said instructions, the method comprising:

identifying, within capability configuration storage, capability configuration information for each of said plurality of exception levels, for each exception level the capability configuration information identifying at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by said capabilities; and

during a switch operation from a source exception level to a target exception level, using the capability configuration information in the capability configuration storage pertaining to at least one of the source exception level and the destination exception level to determine how execution state of the processing circuitry is managed during the switch operation.

22. An apparatus comprising:

processing means for executing instructions, the processing means being operable at a plurality of exception levels, each exception level having different software execution privilege;

a plurality of capability storage element means accessible to the processing means and for storing capabilities used to constrain operations performed by the processing means when executing said instructions; and

capability configuration storage means for identifying capability configuration information for each of said plurality of exception levels, for each exception level the capability configuration information identifying at least whether the operations performed by the processing means when executing instructions at that exception level are constrained by said capabilities; and

during a switch operation from a source exception level to a target exception level, the capability configuration information in the capability configuration storage means pertaining to at least one of the source exception level and the destination exception level is used to determine how execution state of the processing means is managed during the switch operation.