SEMICONDUCTOR DEVICE AND SYSTEMS USING THE SAME

• US 20200133721A1
• Filed: 09/18/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SASAKI, Yasuo
• Granted Patent: US 11,204,799 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)
• CPC Class Codes: G06F 2213/2806 Space or buffer allocation for DMA transfers
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device capable of suppressing performance degradation and systems using the same are provided. The semiconductor device includes a plurality of processors CPU1 and CPU2, a scheduling device 10 (ID1) connected to the processors CPU1 and CPU2 for controlling the processors CPU1 and CPU2 to execute a plurality of tasks in real time, memories 17 and 18 accessed by the processors CPU1 and CPU2 to store data by executing the tasks, and access monitor circuits 15 for monitoring accesses to the memories by the processors CPU1 and CPU2. When an access to the memory is detected by the access monitor circuit 15, the data stored in the memory 18 is transferred based on the destination information of the data stored in the memory 18.

Claims

1. A semiconductor device comprising:

a plurality of first masters;

a scheduling device connected to the plurality of first masters for controlling the plurality of first masters to perform a plurality of tasks in real time;

a memory accessed by the plurality of first masters to store data by performing the tasks; and

an access monitor circuit monitoring access to the memory by the plurality of first masters, wherein when access to the memory is detected by the access monitor circuit, the data stored in the memory is transferred based on destination data.

2. A semiconductor device according to claim 1,

wherein when the access monitor detects that data has been stored in a predetermined address area of the memory, the data stored in the memory is transferred.

3. The semiconductor device according to claim 2, further comprising:

a communication device for transferring data stored in the memory;

the destination information includes identification information specifying a transfer destination of data stored in the memory; and

address information specifying an address area in a memory of a transfer destination specified by the identification information; and

when it is detected that data has been stored in the predetermined address area of the memory, the communication device comprises a second master for transferring data stored in the memory to the address area of the transfer destination specified by the identification information and the address information.

4. The semiconductor device according to claim 3,

wherein the plurality of first masters are processors and the second masters are DMA controllers controlled by the scheduling device, in a semiconductor device.

5. The semiconductor device according to claim 3, further comprising:

a control register including a register in which the destination data is set, and a semiconductor device.

6. The semiconductor device according to claim 1,

wherein when an access to a predetermined address area of the memory is detected by the access monitor circuit, the access monitor circuit updates the state of the control table holding information indicating whether data to be transferred is stored or not and/or information on access time for each address area obtained by subdividing the memory in the address area.

7. The semiconductor device according to claim 6,

wherein the scheduling device selects and preferentially transfers, from among the data stored in each of the segmented address areas, data having a long residence time in the transmission buffer, data referred to by a task having a severe timing constraint, and/or data referred to by a task having a high execution priority, based on information provided from the access monitor circuit.

8. A system comprising a plurality of semiconductor device connected to each other by networks,

wherein each of said plurality of semiconductor device comprises:

a plurality of masters;

a scheduling device connected to the plurality of masters for controlling the plurality of masters to perform a plurality of tasks in real time;

a memory accessed by the plurality of masters to store data by performing tasks; and

an access monitor circuit monitoring access to the memory by the plurality of masters;

wherein when an access to the memory is detected by the access monitor circuit in a first semiconductor device of the plurality of semiconductor device, data stored in the memory is transferred to a second semiconductor device of memory specified by destination data in the plurality of semiconductor device.

9. A system according to claim 8,

wherein the first semiconductor device comprises, as the destination information, identifying information specifying the second semiconductor device from the plurality of semiconductor device and address information specifying a first address area of the second semiconductor device, and in the first semiconductor device, when an access monitor detects that data has been stored in the memory, transfers data stored in the memory to the first address area of the second semiconductor device.

10. A system according to claim 9,

wherein said plurality of semiconductor device comprises a third semiconductor device comprising, as said destination information, identifying information specifying said second semiconductor device and address information specifying a second address area of a memory of said second semiconductor device, and

wherein, in said third semiconductor device, when storage of data in a memory is detected by said access monitor circuitry, data stored in said memory is transferred to said second address area of said second semiconductor device specified by said destination information.

11. The system according to claim 10,

wherein the plurality of masters in the second semiconductor device perform tasks using data transferred from the first semiconductor device and the third semiconductor device.

12. The system according to claim 11,

wherein each of the first semiconductor device, the second semiconductor device and the third semiconductor device further comprises a communication device, and the communication device comprises a master for transferring data between the networks and the memories.

13. The system according to claim 11, further comprising a transmitting device connected to the networks for transmitting data to the first semiconductor device and the third semiconductor device.

14. The system according to claim 10,

wherein each of the first semiconductor device and the third semiconductor device further comprises a control register including a register in which the destination is set.

15. The system according to claim 9,

wherein when the access monitor circuitry in the second semiconductor device detects access to the first address area, the state of the control table holding information indicating whether or not transferred data is stored and/or information on access time is updated for each address area subdivided within the first address area.

16. A system according to claim 9,

wherein the access monitor circuitry in the second semiconductor device provides real-time information about the amount of data that has been transferred from the memory of the first semiconductor device to the first address area of the second semiconductor device to the scheduled device in the second semiconductor device.

17. A system according to claim 9,

wherein the scheduling device in the second semiconductor device activates a task for referencing data transferred to the first address area based on information provided from the access monitor circuit, and/or changes a prioritization order for executing a task for referencing data transferred to the first address area based on information provided from the access monitor circuit.