SEMICONDUCTOR DEVICE

• US 20200133727A1
• Filed: 09/19/2019
• Published: 04/30/2020
• Est. Priority Date: 10/31/2018
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SASAKI, Yasuo
• Granted Patent: US 11,263,046 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/4806 Task transfer initiation or dispatching
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/4887 involving deadlines, e.g. rate based, periodic
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups
• CPC Class Codes: G06F 9/5083 Techniques for rebalancing the load in a distributed system
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A semiconductor device capable of executing a plurality of tasks in real time and improving performances is provided. The semiconductor device comprises a plurality of processors and a plurality of DMA controllers as master, a plurality of memory ways as slave, and a real-time schedule unit for controlling the plurality of masters such that the plurality of tasks are executed in real time. The real-time schedule unit RTSD uses the memory access monitor circuit and the data determination register to determine whether or not the input data of the task has been determined, and causes the task determined to have the input data determined to have been determined to be executed preferentially.

Claims

1. A semiconductor device comprising:

a plurality of masters; and

a real-time schedule unit coupled to the plurality of masters and controlling the plurality of masters to perform a plurality of tasks,

wherein the real-time schedule unit monitors whether input data for the each of tasks has been determined, and activates the task determined to have the input data.

2. The semiconductor device according to claim 1, further comprising:

a slave; and

an access monitor circuit detecting access of the masters to the slave,

wherein the real-time schedule unit monitors whether input data for the each of tasks have been determined based on address signals detected by the access monitor circuit.

3. The semiconductor device according to claim 2, wherein the real-time schedule unit determines that input data for an associated one of the tasks has been determined when address signals detected by the access monitor circuits indicate a predetermined address area.

4. The semiconductor device according to claim 3,

wherein the slave comprises a memory,

wherein the real-time schedule unit detects whether the address signals detected by the access monitor circuits indicate a consecutive predetermined address area in the memory, and

wherein, when the consecutive predetermined address area is indicated, the real-time schedule unit determines that the input data for the associated one of the tasks has been determined.

5. The semiconductor device according to claim 4, further comprising:

a task activation control pointer for setting a head address of the continuous predetermined address area; and

a task activation condition setting register for setting an address information indicating a range of the continuous predetermined address area,

wherein the real-time schedule unit determines that input data required by the associated one of tasks has been determined when an address signal detected by the access monitor circuit indicates all of the continuous predetermined address areas based on the head address and the address information.

6. The semiconductor device according to claim 5, further comprising:

a plurality of task activation control pointers corresponding to the plurality of tasks and a plurality of task activation condition setting registers.

7. The semiconductor device according to claim 6, further comprising:

a task pause condition setting register in which a threshold value for pausing a task is set,

wherein the real-time schedule unit temporarily stops a first task when an address area of the memory which is not read based on a second task exceeds the threshold value stored in the task pause condition setting register in the address area of the memory is written based on the first task.

8. The semiconductor device according to claim 6,

wherein when the size of the input data is less than the size of the continuous predetermined address area,

wherein the data constituting the input data and an end information are stored in the continuous predetermined address area, and

wherein the real-time schedule unit determines, upon detecting the end information, that the input data for the associated one of the tasks has been determined.

9. The semiconductor device according to claim 6,

wherein when the size of the input data is less than the size of the continuous predetermined address area, the data constituting the input data and the predetermined information are stored in the continuous predetermined address area.

10. The semiconductor device according to claim 6,

wherein the input data is divided such that the size of the input data does not exceed the consecutive predetermined address area, when the size of the input data exceeds the consecutive predetermined address area.

11. The semiconductor device according to claim 1, further comprising:

a transfer information obtaining circuit for obtaining the number of cycles accessing the slave from each of the plurality of masters,

wherein the real-time schedule unit changes or/and performs scheduling access routes between the plurality of masters and the slave based on the number of cycles obtained by the transfer information obtaining circuit so that timing constraints are satisfied when there are the timing constraints for performing tasks.

12. The semiconductor device, comprising:

a first and a second master each performing a first task and a second task following the first task;

a real-time schedule unit connected to the first and the second master and controlling the first and the second master to perform the first and the second task in real time, and

wherein the real-time schedule unit monitors whether input data for the second task as an execution result of the first task has been determined,

wherein when the real-time schedule unit detects that a predetermined data size of the input data has been determined, the real-time schedule unit allocates the second task to at least one of the first and the second master.

13. The semiconductor device according to claim 12, wherein data size of the input data for the second task is larger than the predetermined data size.

14. The semiconductor device according to claim 13, wherein the real-time schedule unit allocates the first task to the other one of the first and the second master.

15. The semiconductor device according to claim 12, wherein the first master performs the first task to generate the input data including a first input data and a second input data, when the real-time schedule unit detect the first input data has been determined, the real-time schedule unit allocates the second task corresponding to the first input data to at least one of the first and the second master.