COORDINATING MAIN MEMORY ACCESS OF A PLURALITY OF SETS OF THREADS

• US 20200133732A1
• Filed: 01/02/2020
• Published: 04/30/2020
• Est. Priority Date: 04/03/2017
• Status: Active Application

• Current Assignee: Ocient, Inc.
• Original Assignee: Ocient, Inc.
• Inventors: Kondiles, George, Starr, Rhett Colin
• Application Number:
  US16/732,560
• Publication Number:
  US 20200133732A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 16/24532 of parallel queries
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A computing device includes a plurality of nodes, where a first node operates in accordance with a computing device operation system (OS) and remaining nodes operate in accordance with a custom OS. The remaining nodes include a plurality of sets of processing core resources that process a plurality of sets of threads of an application. The computing device also includes a main memory divided into a computing device memory section and a custom memory section that includes portions logically allocated as a plurality of buffers. The computing device also includes a memory access control module operable to coordinate access to the plurality of buffers by at least some of the plurality of sets of threads in accordance with the custom OS. The computing device also includes disk memory and a disk memory access control module operable to coordinate access to the disk memory in accordance with the computing device OS.

Claims

1. A computing device comprises:

a plurality of nodes, wherein a first node of the plurality of nodes operates in accordance with a computing device operation system (OS) and remaining nodes of the plurality of nodes operate in accordance with a custom OS, wherein the first node includes a set of processing core resources, wherein the remaining nodes include a plurality of sets of processing core resources, and wherein the plurality of sets of processing core resources process a plurality of sets of threads of an application;

a main memory divided into a computing device memory section and a custom memory section, wherein a plurality of portions of the custom memory section is logically allocated as a plurality of buffers and wherein a thread of the plurality of sets of threads is assigned a buffer of the plurality of buffers;

a memory access control module operable to coordinate access to the plurality of buffers by at least some of the plurality of sets of threads in accordance with the custom OS;

disk memory; and

a disk memory access control module operable to coordinate access to the disk memory in accordance with the computing device OS.

2. The computing device of claim 1, wherein the memory access control module is further operable to:

coordinate access to the computing device section of the main memory in accordance with the computing device OS.

3. The computing device of claim 2, wherein the memory access control module is further operable to:

coordinate between the accessing of the computing device section and the accessing of the plurality of buffers.

4. The computing device of claim 1, wherein the memory access control module is further operable to coordinate access to the plurality of buffers by one or more of:

utilizing a thread-safe cross core lock free data flow function;

utilizing an ordered buffer reuse function;

utilizing an out of order input-output re-ordering function; and

utilizing a deadlock free partitioning function.

5. The computing device of claim 1 further comprises:

the custom OS is a database operating system.

6. The computing device of claim 5, wherein the application comprises on of:

a bulk load application;

a data storage application; and

a query response application.

7. The computing device of claim 1, wherein a processing core resource of the processing core resources includes one or more of:

a network interface module;

a memory interface module;

a processing module; and

a cache memory.

8. The computing device of claim 1, wherein the disk memory comprises one or more of:

solid state memory;

disk drive memory; and

non-volatile flash memory.