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COORDINATING MAIN MEMORY ACCESS OF A PLURALITY OF SETS OF THREADS

  • US 20200133732A1
  • Filed: 01/02/2020
  • Published: 04/30/2020
  • Est. Priority Date: 04/03/2017
  • Status: Active Application
First Claim
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1. A computing device comprises:

  • a plurality of nodes, wherein a first node of the plurality of nodes operates in accordance with a computing device operation system (OS) and remaining nodes of the plurality of nodes operate in accordance with a custom OS, wherein the first node includes a set of processing core resources, wherein the remaining nodes include a plurality of sets of processing core resources, and wherein the plurality of sets of processing core resources process a plurality of sets of threads of an application;

    a main memory divided into a computing device memory section and a custom memory section, wherein a plurality of portions of the custom memory section is logically allocated as a plurality of buffers and wherein a thread of the plurality of sets of threads is assigned a buffer of the plurality of buffers;

    a memory access control module operable to coordinate access to the plurality of buffers by at least some of the plurality of sets of threads in accordance with the custom OS;

    disk memory; and

    a disk memory access control module operable to coordinate access to the disk memory in accordance with the computing device OS.

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