PROCESSING OF DATA

• US 20200133763A1
• Filed: 10/25/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Badack, Christian, Trebst, Jessica, Goessel, Michael, Oberlaender, Klaus
• Granted Patent: US 11,556,412 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/102 Error in check bits
• CPC Class Codes: G06F 11/1028 Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/1525 Determination and particular use of error location polynomials
• CPC Class Codes: H03M 13/155 Shortening or extension of codes
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations

Abstract

A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

Claims

1. A method, comprising:

identifying data to be processed; and

processing the data using an error code,

wherein the error code comprises an H-matrix with n columns and m rows,

wherein the columns of the H-matrix are different,

wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix, and

wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

2. The method as claimed in claim 1, wherein a number of all components of a column of the H-matrix is less than the smallest whole number that is greater than 2.log₂ n.

3. The method as claimed in claim 1, wherein the error code is an error-detecting code or an error-correcting and error-detecting code.

4. The method as claimed in claim 1, wherein at least two component-by-component XOR sums of nonadjacent columns of the H-matrix are not different.

5. The method as claimed in claim 1, wherein the error code has a length of n bits with m check bits and n−

m payload bits.

6. The method as claimed in claim 1, further comprising using the error code to:

correct 1-bit errors,

correct adjacent 2-bit errors, and

detect nonadjacent 2-bit errors.

7. The method as claimed in claim 1, further comprising determining a syndrome generator for forming an m-component error syndrome in accordance with the H-matrix.

8. The method as claimed in claim 7, wherein the syndrome generator is implemented as a combinatorial circuit having n inputs and m outputs.

9. The method as claimed in claim 7, further comprising forming correction values for erroneous bit positions using a correction value formation unit that uses the m-component error syndrome provided by the syndrome generator.

10. The method as claimed in claim 1, wherein n≥

2m/².

11. The method as claimed in claim 1, wherein the H-matrix is part of an extended H-matrix.

12. The method as claimed in claim 11, wherein the extended H-matrix is determined by:

duplicating the H-matrix into an original H-matrix and a duplicate H-matrix, wherein an intermediate column having m zeroes is inserted between the original H-matrix and the duplicate H-matrix,

wherein the original H-matrix has two rows having n zeroes added to it,

wherein the duplicate H-matrix has one row having n ones and a further row added to it, wherein the further row is determined by;

a bit combination comprising n bits according to 1010 . . . 10, if n is even-numbered, or

a bit combination comprising n bits according to 1010 . . . 1, if n is odd-numbered, and

wherein the intermediate column comprising m zeroes has one column [0,1]T added to it.

13. The method as claimed in claim 1, wherein the H-matrix is adapted by deleting at least one first column and/or at least one last column.

14. The method as claimed in claim 1, wherein the H-matrix is modified by a linear combination of its rows.

15. The method as claimed in claim 1, wherein the processing of the data comprises writing to a memory or reading from a memory.

16. An apparatus for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the apparatus comprises:

a memory circuit comprising instructions; and

a processing circuit that is configured to retrieve and execute the instructions, and upon execution of the instructions is configured to;

determine the error code in accordance with the H-matrix,

wherein the columns of the H-matrix are different,

wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix, and

wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

17. The apparatus as claimed in claim 16, wherein the processing circuit comprises a syndrome generator configured to output syndromes based on the H-matrix.

18. The apparatus as claimed in claim 16, wherein the processing of the data comprises writing to the memory or reading from the memory.

19. The apparatus as claimed in claims 16, wherein a number of all components of a column of the H-matrix is less than the smallest whole number that is greater than 2.log₂ n.

20. The apparatus as claimed in claim 16, wherein at least two component-by-component XOR sums of nonadjacent columns of the H-matrix are not different.