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ANTI-TEARING PROTECTION SYSTEM FOR NON-VOLATILE MEMORIES

  • US 20200133765A1
  • Filed: 10/17/2019
  • Published: 04/30/2020
  • Est. Priority Date: 10/31/2018
  • Status: Active Grant
First Claim
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1. Anti-tearing protection system (1) of a non-volatile memory unit (3), which comprises a first memory block (5) and a second memory block (7), the first and second memory blocks (5, 7) being intended to store a data set comprising user data and an error detection code obtained based on the user data, the first and second memory blocks (5, 7) being arranged to be read in a first read mode defining a first rule set for determining logic states of data elements comprised in the data set according to the first read mode, the user data in a respective memory block are considered to be correct according to the first read mode if its error detection code equals a first given value, said first rule set comprising a first memory read threshold (13),the system being characterised in that the first and second memory blocks (5, 7) being further arranged to be read in a second read mode defining a second rule set for determining the logic states of the data elements comprised in the data set according to the second read mode, said second rule set comprising a second memory read threshold (15), wherein a processing unit (9) of the system (1) is configured to read both the first and second memory blocks (5, 7), and wherein in the processing unit (9), the user data in a respective memory block are considered to be correct according to the second read mode if its error detection code equals the first given value and if the user data as read in the second read mode are determined to be identical to the user data as read in the first read mode, wherein the data set further comprises counter data indicating which memory block (5, 7) was updated last, and wherein the error detection code is further obtained based on the counter data, and wherein the correctness of the user data is arranged to be used for determining which one of the first and second memory blocks (5, 7) should be updated next by a memory write unit (11) of the system (1).

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