SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND MEMORY SYSTEM
First Claim
1. A semiconductor memory device comprising:
- a row decoder configured to decode a row address to generate a word line selection signal;
a column decoder configured to decode a column address to generate a column selection signal;
a memory cell array comprising a plurality of memory cells, one or more memory cells selected in response to the word line selection signal and the column selection signal; and
an error correcting code (ECC) decoder configured to receive first data and a parity output from the selected memory cells of the memory cell array and generate a syndrome based on the first data and the parity, and in response to a read operation of the semiconductor memory device being performed, to generate second data and a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome and to output the second data and the DSF to an external device outside of the semiconductor memory device,wherein a number of bits of the first data is the same as a number of bits of the second data.
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Accused Products
Abstract
Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.
1 Citation
20 Claims
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1. A semiconductor memory device comprising:
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a row decoder configured to decode a row address to generate a word line selection signal; a column decoder configured to decode a column address to generate a column selection signal; a memory cell array comprising a plurality of memory cells, one or more memory cells selected in response to the word line selection signal and the column selection signal; and an error correcting code (ECC) decoder configured to receive first data and a parity output from the selected memory cells of the memory cell array and generate a syndrome based on the first data and the parity, and in response to a read operation of the semiconductor memory device being performed, to generate second data and a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome and to output the second data and the DSF to an external device outside of the semiconductor memory device, wherein a number of bits of the first data is the same as a number of bits of the second data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A controller comprising:
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an error correcting code (ECC) decoder configured to; perform an ECC decoding operation selected from among a plurality of ECC decoding operations on first data applied from an external device outside of the controller in response to a decoding status flag (DSF) applied from the external device and indicating a type of an error of the first data, and generate second data and an error signal by performing the selected ECC decoding operation, wherein the first data and the DSF are provided from an outside of the controller, and wherein a number of bits of the first data is the same as a number of bits of the second data. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A memory system comprising:
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a semiconductor memory device comprising; a row decoder configured to decode a row address to generate a word line selection signal; a column decoder configured to decode a column address to generate a column selection signal; a memory cell array comprising a plurality of memory cells, one or more memory cells are selected in response to the word line selection signal and the column selection signal; and a first error correcting code (ECC) decoder configured to; perform a first ECC decoding operation by receiving first data and a parity output from selected memory cells of the memory cell array, generate a syndrome based on the first data and the parity, generate second data by performing the first ECC decoding operation, and generate a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome when a read operation of the semiconductor memory device is performed; and a controller configured to control the semiconductor memory device, the controller comprising; a second ECC decoder configured to perform an ECC decoding operation selected from among a plurality of ECC decoding operations on the second data applied from the semiconductor memory device in response to the DSF applied from the semiconductor memory device. - View Dependent Claims (17, 18, 19, 20)
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Specification