STORAGE DEVICE AND METHOD OF OPERATING THE SAME

• US 20200133806A1
• Filed: 05/28/2019
• Published: 04/30/2020
• Est. Priority Date: 10/25/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: HER, Min Ho, KIM, Dong Hyun, KIM, Seung Il, JUNG, Youn Ho
• Granted Patent: US 11,422,905 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 2201/85 Active fault masking without idle spares active fault masking without idle spare hardware where processing functionality is redundant G06F11/2035
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A memory controller controls a memory device including a plurality of memory blocks and a plurality of power modules respectively providing voltages to a plurality of word line groups, the memory controller comprising: a fail block detector detecting fail blocks on which an erase operation has failed among the plurality of memory blocks, and detecting fail word line groups among a plurality of word line groups included in each of the fail blocks; a fail block manager detecting, among the plurality of power modules, a defective power module providing the voltages to two or more fail word line groups each included in a different fail block among the fail blocks; and a power defect controller controlling the memory device such that the defective power module is changed to another power module among the plurality of power modules.

Claims

1. A memory controller configured to control a memory device including a plurality of memory blocks each including a plurality of word line groups each coupled to a plurality of memory cells and a plurality of power modules configured to respectively provide voltages to the plurality of word line groups, the memory controller comprising:

a fail block detector configured to detect fail blocks on which an erase operation has failed among the plurality of memory blocks, and detect fail word line groups among a plurality of word line groups included in each of the fail blocks;

a fail block manager configured to detect, among the plurality of power modules, a defective power module providing the voltages to two or more fail word line groups each included in a different fail block among the fail blocks; and

a power defect controller configured to control the memory device such that the defective power module is changed to another power module among the plurality of power modules.

2. The memory controller according to claim 1,

wherein the fail block detector performs an erase verify operation of applying an erase verify voltage to the plurality of word line groups included in a selected memory block, among the plurality of memory blocks, and determines the selected memory block as a fail block, when a number of fail bits in the selected memory block exceeds a preset value in the erase verify operation, and

wherein the number of fail bits indicates the number of memory cells having higher threshold voltage than the erase verify voltage, among a plurality of memory cells included in the selected memory block.

3. The memory controller according to claim 1,

wherein the fail block detector performs an erase verify operation of applying an erase verify voltage to the plurality of word line groups included in a selected memory block, among the plurality of memory blocks, determines the selected memory block as a fail block, when at least one of the plurality of word line groups included in the selected memory block includes a fail word line, and

wherein the fail word line is a word line in which a number of fail bits exceeds a preset value as a result of the erase verify operation, and

wherein the number of fail bits indicates the number of memory cells having higher threshold voltage than the erase verify voltage among a plurality of memory cells coupled to the fail word line.

4. The memory controller according to claim 3, wherein the fail block detector generates fail block information indicating whether each of the plurality of word line groups included in the fail block is a fail word line group including the fail word line.

5. The memory controller according to claim 4,

wherein the fail block manager stores a fail block table configured to include the fail block information, and

wherein when two or more fail word line groups each included in a different fail block are provided with voltages from a same power module based on the fail block table, the fail block manager generates power defect information indicating that the same power module is the defective power module.

6. The memory controller according to claim 1, wherein the defective power module is a power module among the plurality of power modules, that provides voltages to the two or more fail word line groups each included in a different fail block.

7. The memory controller according to claim 1, wherein the another power module is a power module that provides voltages to word line groups that are different from and adjacent to the two or more fail word line groups each included in the different fail block.

8. The memory controller according to claim 1, wherein the power defect controller provides to the memory device a set parameter command for controlling the memory device to change the defective power module to the another power module.

9. A memory device comprising:

a memory cell array including a plurality of memory blocks each including a plurality of word line groups each coupled to a plurality of memory cells;

a voltage generator including a plurality of power modules configured to respectively provide voltages to the plurality of word line groups;

a power routing table configured to include power routing information indicating relationships between the plurality of word line groups and the plurality of power modules; and

a control logic configured to perform an erase operation on the plurality of memory blocks,

wherein the control logic sets the power routing table under control of an external controller such that a defective power module providing the voltages to two or more fail word line groups each included in a different fail block among fail blocks is changed to another power module among the plurality of power modules, and

wherein the fail blocks are memory blocks among the memory blocks on which an erase operation has failed.

10. The memory device according to claim 9,

wherein the control logic performs, under control of the external controller, an erase verify operation of applying an erase verify voltage to the plurality of word line groups included in the plurality of memory blocks, and

wherein the two or more fail word line groups are word line groups on which the erase verify operation has failed among the plurality of word line groups included in the plurality of memory blocks.

11. A memory controller configured to control a memory device including a plurality of memory blocks each including a plurality of word line groups each coupled to a plurality of memory cells;

and a plurality of power modules configured to respectively provide voltages to the plurality of word line groups, the memory controller comprising;

a fail block detector configured to detect a fail block including a fail word line on which an program operation has failed, among the plurality of memory blocks, and detect fail word line group including the fail word line, among a plurality of word line groups included in the fail block;

a fail block manager configured to detect, among the plurality of power modules, a defective power module providing the voltages to two or more fail word line groups each included in a different fail block among a plurality of fail blocks; and

a power defect controller configured to control the memory device such that the defective power module is changed to another power module among the plurality of power modules.

12. The memory controller according to claim 11, wherein the fail block detector performs a program verify operation of applying a program verify voltage to a word line on which the program operation has performed.

13. The memory controller according to claim 12, wherein the fail word line is a word line in which a number of fail bits exceeds a preset value as a result of the program verify operation, and

Wherein the number of fail bits indicates the number of memory cells having higher threshold voltage than the program verify voltage among a plurality of memory cells coupled to the fail word line.

14. The memory controller according to claim 13, wherein the fail block detector generates fail block information indicating whether each of the plurality of word line groups included in the fail block is the fail word line group.

15. The memory controller according to claim 14,

wherein the fail block manager stores a fail block table configured to include the fail block information of the plurality of fail blocks, and

wherein when two or more fail word line groups each included in a different fail block are provided with voltages from the same power module based on the fail block table, the fail block manager generates power defect information indicating that the same power module is the defective power module.

16. The memory controller according to claim 11, wherein the defective power module is a power module among the plurality of power modules, that provides voltages to the two or more fail word line groups each included in a different fail block.

17. The memory controller according to claim 11, wherein the power defect controller provides to the memory device a set parameter command for controlling the memory device to change the defective power module to the another power module.

18. A memory device comprising:

a memory cell array including a plurality of memory blocks each including a plurality of word line groups each coupled to a plurality of memory cells;

a voltage generator including a plurality of power modules configured to respectively provide voltages to the plurality of word line groups;

a power routing table configured to include power routing information indicating relationships between the plurality of word line groups and the plurality of power modules; and

a control logic configured to perform a program operation on a plurality of word lines included in each of the plurality of memory blocks,

wherein the control logic sets the power routing table under control of an external controller such that a defective power module providing the voltages to two or more fail word line groups each included in a different fail block among a plurality of fail blocks is changed to another power module among the plurality of power modules, and

wherein a fail block includes a fail word line on which the program operation has failed, and

wherein a fail word line group is a word line group including the fail word line, among the plurality of word line groups included in the fail block

19. The memory device according to claim 18, wherein the another power module is, among the plurality of power modules, a power module that provides a voltage to a word line group that is different from and adjacent to the two or more fail word line groups each included in the different fail block.

20. A memory system comprising:

a memory device including;

a plurality of memory blocks each coupled to a plurality of word line groups; and

a plurality of power modules configured to provide one or more voltages to the memory blocks through the word line groups, respectively; and

a controller configured to;

control the memory device to perform data-change operations on the memory blocks by using the voltages; and

control the memory device to replace a defective power module with a normal power module among the power modules, when the data-change operations fail on memory cells coupled to two or more fail word line groups within two or more fail blocks among the memory blocks and the fail word line groups each included in a different fail block among the fail blocks are provided with the voltages from the defective power module among the power modules.