Data processing method for memory and related data processor

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First Claim
1. A data processing method, comprising:
 dividing a page of bit data into a plurality of groups;
counting the number of a first bit value and the number of a second bit value in each of the plurality of groups;
comparing the number of the first bit value and the number of the second bit value;
performing a reshaping procedure on each of the plurality of groups based on the result of comparing the number of the first bit value and the number of the second bit value; and
storing the page of bit data in memory after the reshaping procedure;
wherein the reshaping procedure comprises at least one of;
reversing the bit data in a first group among the plurality of groups when the number of the first bit value is greater than the number of the second bit value in the first group; and
keeping the bit data in a second group among the plurality of groups when the number of the first bit value is less than the number of the second bit value in the second group; and
wherein bit values corresponding to a state distribution in a plurality of memory cells of the memory are encoded to allow the second bit value to be more concentrated on middle states of the state distribution than the first bit value.
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Abstract
The present invention provides a data processing method for a memory and a related data processor for performing the method. A page of data may be divided into multiple groups. In each group, the number of “1”s and the number of “0”s are determined, so as to determine whether to reverse or keep the bit data in the group. The encoding scheme may make the bit value “0” more concentrated on the middle states of the state distribution than the bit value “1”. The data processor thereby reverses the bit data in a group if the number of “1”s is greater than the number of “0”s in the group, and keeps the bit data in a group if the number of “1”s is less than the number of “0”s in the group. As a result, the occurrence probability of the states at two sides becomes lower and the occurrence probability of the middle states becomes higher. This improves data retention of the memory.
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16 Claims
 1. A data processing method, comprising:
dividing a page of bit data into a plurality of groups; counting the number of a first bit value and the number of a second bit value in each of the plurality of groups; comparing the number of the first bit value and the number of the second bit value; performing a reshaping procedure on each of the plurality of groups based on the result of comparing the number of the first bit value and the number of the second bit value; and storing the page of bit data in memory after the reshaping procedure; wherein the reshaping procedure comprises at least one of; reversing the bit data in a first group among the plurality of groups when the number of the first bit value is greater than the number of the second bit value in the first group; and keeping the bit data in a second group among the plurality of groups when the number of the first bit value is less than the number of the second bit value in the second group; and wherein bit values corresponding to a state distribution in a plurality of memory cells of the memory are encoded to allow the second bit value to be more concentrated on middle states of the state distribution than the first bit value.  View Dependent Claims (3, 4, 6, 7, 8)
 2. (canceled)
 5. (canceled)
 9. A data processor for processing bit data, the data processor comprising:
a receiver, for receiving a page of bit data; and a processing unit, for performing the following units; dividing unit, for dividing the page of bit data into a plurality of groups; counting unit, for counting the number of a first bit value and the number of a second bit value in each of the plurality of groups; comparing unit, for comparing the number of the first bit value and the number of the second bit value; performing unit, for performing a reshaping procedure on each of the plurality of groups based on the result of the comparing unit; and storing unit, for storing the page of bit data in memory after the reshaping procedure; wherein the performing unit further comprises the following units; reversing unit, for reversing the bit data in a first group among the plurality of groups when the number of the first bit value is greater than the number of the second bit value in the first group; and keeping unit, for keeping the bit data in a second group among the plurality of groups when the number of the first bit value is less than the number of the second bit value in the second group; and wherein bit values corresponding to a state distribution in a plurality of memory cells of the memory are encoded to allow the second bit value to be more concentrated on middle states of the state distribution than the first bit value.  View Dependent Claims (11, 12, 14, 15, 16)
 10. (canceled)
 13. (canceled)
1 Specification
The present application is a continuation application of International Application No. PCT/CN2018/112149, filed on Oct. 26^{th}, 2018. The present application is based on and claims priority to International Application No. PCT/CN2018/112149, filed on Oct. 26^{th}, 2018, the contents of which are incorporated herein by reference in its entirety.
The present invention relates to a data processing method for a memory, and more particularly, to a data processing method for a quadlevel cell (QLC) NAND flash memory.
A nonvolatile memory is a type of computer memory that may store data and the data may not be lost after electric power of the computer system is cut off. Among those nonvolatile memory systems, the NAND flash memory, which has advantages of low power and high speed, becomes popular with the widespread use of portable devices in recent years.
The NAND flash memory stores data in individual memory cells. Traditionally, each memory cell has two possible states, so one bit of data is stored in each cell, which makes up a socalled singlelevel cell (SLC) flash memory. The SLC memory has the advantages of higher write speed, lower power consumption and higher cell endurance capability. Since the SLC flash memory stores only one bit data per cell, it costs more to manufacture a unit of storage space. In order to reduce the cost, NAND flash vendors constantly dedicate their efforts to increase storage density, and the multibitcell (MBC) flash memory such as a multilevel cell (MLC) flash memory is therefore generated. The “MBC” refers to a memory element capable of storing more than one single bit of data. The MBC flash is a flash memory technology using multiple levels per cell to allow more bits to be stored using the same number of transistors.
In the SLC flash technology, each cell can exist in one of two states, storing one bit of data per cell. In comparison, the MLC flash memory has four possible states per cell, so it can store two bits of data per cell. Due to the higher data density of the MLC flash memory, it can enjoy the benefit of lower cost per bit of stored data. However, the MLC flash technology reduces the amount of margin separating the states, which results in the increased possibility of errors. Nowadays, the triplelevel cell (TLC) and quadlevel cell (QLC) flash memories are developed, where each cell is configured to store 3 and 4 bits of data, respectively. For example, in a QLC NAND flash memory, one cell may store 4 bits of data; hence, the cell may be in one of 16 different states, as denoted by E (also called D0), D1, D2, . . . and D15.
In a charge trapping type NAND flash memory, all memory cells in one channel hole share the same charge trapping layer (CTL) . Please refer to
In the prior art, the NAND flash system does not deal with this problem. The NAND flash system merely randomizes input data and then stores the randomized data, where the randomization procedure cannot change the occurrence probability of (E, D15) or (D15, E) state arrangement, and thus cannot improve the data retention problem. Thus, there is a need for improvement over the prior art.
It is therefore an objective of the present invention to provide a data processing method which is capable of reducing the occurrence probability of state combination (E, D15) or (D15, E) in two adjacent cells in one channel hole, in order to mitigate the data retention problem.
An embodiment of the present invention discloses a data processing method. The data processing method comprises dividing a page of bit data into a plurality of groups; counting the number of a first bit value and the number of a second bit value in each of the plurality of groups; comparing the number of the first bit value and the number of the second bit value; performing a reshaping procedure on each of the plurality of groups based on the result of comparing the number of the first bit value and the number of the second bit value; and storing the page of bit data in memory after the reshaping procedure.
Another embodiment of the present invention discloses a data processor for processing bit data. The data processor comprises a receiver and a processing unit. The receiver is configured for receiving a page of bit data. The processing unit is configured for performing the following units: dividing unit, for dividing the page of bit data into a plurality of groups; counting unit, for counting the number of a first bit value and the number of a second bit value in each of the plurality of groups; comparing unit, for comparing the number of the first bit value and the number of the second bit value; performing unit, for performing a reshaping procedure on each of the plurality of groups based on the result of the comparing unit; and storing unit, for storing the page of bit data into memory after the reshaping procedure.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Please refer to
As mentioned above, when two adjacent memory cells in one channel hole store different states, the electrons and holes in the charge trapping layer (CTL) may drift to adjacent cells, especially when there are state combination (E, D15) or (D15, E) stored in two adjacent cells. This results in data retention problem. The present invention solves this problem through a data processing technique which reduces the occurrence probability of the states “E” and “D15”, which in turn reduces the probability that the state combination (E, D15) or (D15, E) appears to be stored in two adjacent cells.
Please refer to
The data processor 310 of the present invention will process the input data and reshape the state distribution to be similar to that shown in
More specifically, the state distribution shown in
As shown in Table 1, the bit value “0” is more concentrated on the middle states (near “D6”) while the bit value “1” is more concentrated on the twoside states (near “E” and “D15”). In this embodiment, the memory 320 is a QLC NAND flash memory, and thus each memory cell in the memory 320 is configured to store 4 bits of data, and these 4 bits of data belong to 4 pages of bit data, e.g., Page 1 to Page 4 shown in Table 1. For each memory cell, the combination of 4 bit values “1” and/or “0” in the corresponding bit of Page 14 is mapped to one of the states from “E” to “D15”. For example, if the bit values stored in a memory cell are “1”, “1”, “1” and “1” corresponding to Page 1, Page 2, Page 3 and Page 4, respectively, the state of this memory cell may be “E”. If the bit values stored in a memory cell are “1”, “0”, “1” and “1” corresponding to Page 1, Page 2, Page 3 and Page 4, respectively, the state of this memory cell may be “D1”.
According to the encoding scheme shown in Table 1, the bit value “0” is more concentrated on the middle states and the bit value “1” is more concentrated on the twoside states. In order to decrease the occurrence probability of the twoside states and increase the occurrence probability of the middle states, the data stored in the memory 320 should include “0”s as more as possible, i.e., include “1”s as less as possible. However, under most circumstances, the bit data received from a user or from other device may not be determined by the data processor 310, such that the numbers of received “1”s and “0”s cannot be predetermined. In order to store “0”s as more as possible, the data processor 310 may divide the received data into small groups, count the “1”s and “0”s in each group, and reverse the bit data in a group if the number of “1”s is greater than the number of “0”s in the group, so as to generate more “0”s in the data to be stored in the memory 320.
In detail, please refer to
Step 500: Start.
Step 502: Divide a page of bit data into a plurality of groups.
Step 504: Count the number of a first bit value and the number of a second bit value in each of the plurality of groups.
Step 506: Determine whether the number of the first bit value is greater than the number of the second bit value in each group among the plurality of groups. If yes, go to Step 508; otherwise, go to Step 512.
Step 508: Reverse the bit data in the group.
Step 510: Generate a flag indicating that the bit data in the group are reversed.
Step 512: Remain the bit data in the group.
Step 514: Generate a flag indicating that the bit data in the group are remained.
Step 516: End.
According to the data processing process 50 together with the structure of the data processor 310 shown in
In general, a page of data may include several kilobytes or several tens of kilobytes of bit data, where the data quantity in a page is quite large. With larger data quantity, the ratio of “0”s in a page may be closer to 50% more probably; hence, the method of reversing the bit data in an entire page may not gain a preferable benefit with increase of the number of “0”s. In such a situation, each page of data is divided into multiple groups, and the determinations of the numbers of “1”s and “0”s are performed individually for each group. The size of a group may be 64 bits, 128 bits, or any other feasible value. With the smaller size in each group, there may be a significant difference between the number of “1”s and the number of “0”s in each group.
Please note that for each group, a flag may be generated or assigned to indicate that the bit data in this group are reversed or remained in the reshaping procedure. In an embodiment, the flag may be realized with a bit, where the bit value “1” indicates that the bit data is reversed and “0” indicates that the bit data is remained, or the bit value “0” indicates that the bit data is reversed and “1” indicates that the bit data is remained. The flag may also be stored in the memory 320 together with the corresponding group of data.
Please note that the present invention aims at providing a data processing method for mitigating the data retention problem in a flash memory. Those skilled in the art may make modifications and alternations accordingly. For example, the above embodiments are dedicated to the QLC NAND flash memory since the data retention problem may be more severe in the QLC NAND flash memory in modern flash memory technology. However, those skilled in the art should understand that the data processing method and the data processor of the present invention are also applicable to other type of memories such as the triplelevel cell (TLC) flash memory. In addition, the encoding method illustrated in Table 1 is only one of various implementations of the present invention. Another encoding scheme is also feasible if it encodes the bit values to make a first bit value more concentrated on the middle states and make a second bit value more concentrated on the twoside states. For example, as shown in Table 2 and Table 3, the bit value “0” is also more concentrated on the middle states than the bit value “1”, and the encoding scheme may be incorporated with the data processing method of the present invention to reduce the probability that the state combination (E, D15) or (D15, E) appears in two adjacent cells in the same channel hole.
Further, in another embodiment, the encoding scheme may make the bit value “1” more concentrated on the middle states and make the bit value “0” more concentrated on the twoside states. In such a situation, the bit data in a group may be reversed if the number of “0”s is greater than the number of “1”s in the group, and the bit data in a group may be remained if the number of “0”s is less than the number of “1”s in the group. Therefore, the state distribution maybe reshaped to decrease the occurrence probability of the twoside states by increasing the number of “1”s and decreasing the number of “0” stored in the memory cells.
To sum up, the present invention provides a data processing method for a memory such as a QLC NAND flash memory. Before the data is stored in the memory, the data is processed by a data processor. The data processor may divide a page of data into multiple groups, and determine the number of “1”s and the number of “0”s in each group, so as to determine whether to reverse or remain the bit data in the group. In an embodiment, the encoding scheme makes the bit value “0” more concentrated on the middle states of the state distribution than the bit value “1”. The data processor thereby reverses the bit data in a group if the number of “1”s is greater than the number of “0”s in the group, and remains the bit data in a group if the number of “1”s is less than the number of “0”s in the group. As a result, the occurrence probability of the states at two sides becomes lower and the occurrence probability of the middle states becomes higher, which reduces the probability that the state combination (E, D15) or (D15, E) appears in two adjacent cells. Therefore, the data retention problem of the memory may be mitigated.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.