MEMORY CONTROLLER AND MEMORY SYSTEM

• US 20200133837A1
• Filed: 09/03/2019
• Published: 04/30/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: TDK Corporation
• Original Assignee: TDK Corporation
• Inventors: MUKAIDA, Naoki, TAKUBO, Kenichi
• Granted Patent: US 11,249,895 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A memory controller for preventing the storage area of a flash memory being reduced is provided. The memory controller controlling access to a flash memory based on a command provided from a host system, the memory controller includes: a processor, a RAM (random access memory), and a mask ROM (read only memory) in which a first firmware is written, wherein the memory controller is configured to: perform a search for a second firmware written in the flash memory based on the first firmware at a start-up time; and write a third firmware provided from the host system in the RAM when the second firmware is not found through the search and perform an initialization based on the third firmware written in the RAM.

Claims

1. A memory controller for controlling access to a flash memory based on a command provided from a host system, the memory controller comprising:

a processor;

a RAM (random access memory); and

a mask ROM (read only memory) in which a first firmware is written,

wherein the memory controller is configured to;

perform a search for a second firmware written in the flash memory based on the first firmware at a start-up time; and

write a third firmware provided from the host system in the RAM when the second firmware is not found through the search and perform an initialization based on the third firmware written in the RAM.

2. The memory controller according to claim 1, wherein processing performed in the initialization includes a process to designate an area in which the second firmware is written in a storage area of the flash memory and a process to write the second firmware provided from the host system in the designated area.

3. The memory controller according to claim 1, wherein the memory controller is configured to:

transmit error information to the host system when the second firmware is not found through the search; and

be provided the third firmware from the host system after receiving a command that the host system transmit firmware to the memory controller.

4. The memory controller according to claim 2, wherein the memory controller is configured to:

transmit error information to the host system when the second firmware is not found through the search; and

be provided the third firmware from the host system after receiving a command that the host system transmit firmware to the memory controller.

5. The memory controller according to claim 2, wherein the memory controller is configured to

start operation on the basis of the second firmware after the initialization is performed.

6. The memory controller according to claim 4, wherein the memory controller is configured to

start operation on the basis of the second firmware after the initialization is performed.

7. A memory system comprising:

a flash memory; and

a memory controller configured to control access to the flash memory based on a command provided from a host system,

wherein the memory controller comprises;

a processor;

a RAM (random access memory); and

a mask ROM (read only memory) in which a first firmware is written,

wherein the memory controller is configured to;

perform a search for a second firmware written in the flash memory based on the first firmware at a start-up time; and

write a third firmware provided from the host system in the RAM when the second firmware is not found through the search and perform an initialization based on the third firmware written in the RAM.

8. The memory system according to claim 7, wherein processing performed in the initialization includes a process to designate an area in which the second firmware is written in a storage area of the flash memory and a process to write the second firmware provided from the host system in the designated area.

9. The memory system according to claim 7, wherein the memory controller is configured to:

transmit error information to the host system when the second firmware is not found through the search; and

be provided the third firmware from the host system after receiving a command that the host system transmit firmware to the memory controller.

10. The memory system according to claim 8, wherein the memory controller is configured to:

transmit error information to the host system when the second firmware is not found through the search; and

be provided the third firmware from the host system after receiving a command that the host system transmit firmware to the memory controller.

11. The memory system according to claim 8, wherein the memory controller is configured to

start operation on the basis of the second firmware after the initialization is performed.

12. The memory system according to claim 10, wherein the memory controller is configured to

start operation on the basis of the second firmware after the initialization is performed.